Advance Computer Architecture Mcq's

Set-1
Q. A typical system bus consists of approximately................signals

lines
(a) 100
(b) 2
(c) 3
(d) None of the above

Q. A bus that connects components in a multiprocessor system, is
called:
(a) Control bus
(b) Data bus
(c) Address bus
(d) System bus

Q. The ...........................organization consists of number of cross
points that are placed at intersection between buses and memory
module paths
(a) Multiport memory
(b) Crossbar switch
(c) Multistage switch

Q. The memory connected to the common system bus
is.......................by all processors.
(a) Shared
(b) Partitioned
(c) Distributed

Q. In a ......................has it own private local memory
(a) Crossbar switch
(b) Tightly coupled system
(c) Loosely coupled system

Q. Loosely coupled system are more efficient when the interaction
between task is:
(a) Maximum
(b) Minimum
(c) Can not say

Q. A multiprocessor system with common shared memory is
called:
(a) Loosely coupled system
(b) Tightly coupled system
(c) Both a and b

Q. Computers are interconnected with each other by means of
communication lines to form a:
(a) Computer Network
(b) Multiprocessor
(c) Data Dependency

Q. The components that form a multiprocessor system are:
(a) CPUs
(b) IOPs
(c) Memory Unit
(d) All of the above

Q. MIMD stands for:
(a) More Instruction Stream, Multiple data Stream
(b) Multiple Instruction Stream, Multiple Data Stream
(c) Many Instruction Stream, Many Data Stream

Q. A.......................system is an interconnection of two more CPU
with memory and I/O equipment.
(a) Processor
(b) Synchronization
(c) Multiprocessor

Q. Many operating system are designed to enable the CPU to
process a number of independent program concurrently. This
concept is called:
(a) Cache Memory
(b) Multiprogramming
(c) Multiprocessor

Q. A......................is an interconnected set of processing elements
which cooperate by communicating with one another to solve
large problem
(a) Parallel Computer
(b) Personal Computer
(c) Laptop Computer

Q. A.............contains the address of the next instructions to be
executed.
(a) Data Register
(b) Accumulator
(c) Instruction Register
(d) Program Counter

Q. Personal computer were appeared in:
(a) Ist generation
(b) 2nd generation
(c) 4th generation
(d) 5th generation

Q. ...............................is a technique of decomposing a sequential
process into sub operations.
(a) Pipelining
(b) Parallel Processing
(c) Vector Processing

Q. ........................is a term used to denote a large class of
techniques that are used to provide simultaneous data processing
tasks
(a) Shared memory
(b) Parallel Processing
(c) Memory hierarchy
Q. CISC stands for:
(a) Clock Instruction Set Computer
(b) Control Instruction Set Computer
(c) Complex Instruction Set Computer

Q. CISC processor have...............length instruction format.
(a) Variable
(b) Fixed
(c) Can not say

Q. RISC stands for:
(a) Register Instruction Set Computer
(b) Reduced Instruction Set Computer
(c) Reduced Instruction Set Clock

Set-2

Q. The process of assigning control of the data transfer bus to a
requester is called:
(a) Interleaving
(b) Interruption
(c) Synchronization
(d) Arbitration

Q. MAL stands for:
(a) Minimal Average Latency
(b) Minimum Allocation Latency
(c) Maximum Allocation Latency
(d) Maximum Average Latency

Q. Which of the example of blocking network?
(a) Baseline
(b) Delta
(c) Omega

Q. Which are the valid vector access memory schemes?
(a) C-access Memory Organization
(b) Synchronous Memory Organization
(c) D-Access memory organization
(d) Asynchronous memory organization

Q. To find out cache performance, we can use:
(a) Program trace driven simulation
(b) Hit Ratio
(c) Creedy Cycles
(d) Cycle count

Q. Which is not a valid data routing function?
(a) Perfect shuffle and exchange
(b) Permutation
(c) Multicast
(d) Broadband

Q. .................is a shared memory system in which the access time
varies with the location of the memory word:
(a) COMA
(b) UMA
(c) NUMA

Q. ..................networks are controlled by a global clock
(a) Asynchronous
(b) Synchronous
(c) Both of the above

Q. The major disadvantage of pipeline is:
(a) High cost individual dedicated
(b) Initial setup time
(c) If branch instruction is encountered the pipe has to be flushed

Q. VLIW stands for:
(a) Vector Large Instruction Word
(b) Very Long Instruction Word
(c) Very Large Integrated Word
(d) Very Low Integrated Word

Q. a crossbar switch network is a :
(a) Regular connection network
(b) Irregular connection network
(c) Static connection network
(d) Dynamic connection network
Q. Multiprocessor is one with:
(a) One CPU executing several processors
(b) One CPU and several channels
(c) Several CPU

Q. The size of program is determined of:
(a) Clock Rate
(b) Clock Count
(c) Instruction Execution Rate
(d) Instruction count

Q. The diameter of a network is the:
(a) Maximum shortest path between any two nodes
(b) Minimum shortest path between any two nodes
(c) Minimum shortest path between any two adjacent nodes
(d) Minimum longest path between any two adjacent nodes

Q. The topology of an interconnection network can be:
(a) Static
(b) Dynamic
(c) Either (a) and (b)

Q. TLB is used in:
(a) Paging
(b) Segmentation

Q. If the number of links is 2N, then this would be which kind of
network?
(a) Illiac mesh
(b) 2D mesh

Q. The time required for two processes to synchronize with each
other is called:
(a) Synchronization time
(b) Synchronization Latency
(c) Process Latency
(d) Memory Latency

Q. The channel width of a ..............network increases as we ascend
from leaves to the root.
(a) Binary fat tree
(b) Star
(c) Ring
(d) Binary tree

Set-3
Q. An/a .....................is a request from I/O or other devices to a
processor for services or attention:
(a) Interrupt
(b) Transaction
(c) Arbitration

Q. ..........................computing is achieved through the use of an
array of processing elements synchronized by the same controller;
(a) MIMD
(b) SIMD

Q. Processors that use multiphase clock with a much increases
clock rate ranging from 100 to 500 MHz.
(a) RISC
(b) VLIW

Q. In general vector processing is faster and.................scalar
processing:
(a) Less efficient than
(b) Equally efficient to
(c) More efficient than

Q. DOP stands for:
(a) Dual Operating
(b) Dual of Parallelism
(c) Degree of processing
(d) Degree of Parallelism

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What are the different types of multiprocessor systems discussed in the document?

What are some key characteristics of vector processing compared to scalar processing?

Set-1

Q. A typical system bus consists of approximately................signals

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