Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology

Larry Smith, Raymond Anderson, Doug Forehand, Tom Pelc, Tanmoy Roy Sun Microsystems, Inc. MS MPK15-103 901 San Antonio Rd, Palo Alto, CA 94303-4900 [email protected], Fax: (650) 786 6457

Abstract
Power Systems for modern CMOS technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance vs. frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to spice models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor ESR and ESL are extremely important parameters in determining how many capacitors are required. Spice models are then analyzed in the time domain to find the response to load transients.

Introduction
Design of the Power Distribution System (PDS) is becoming an increasingly difficult challenge for modern CMOS technology. As CMOS technology is scaled to give smaller and faster transistors, the power supply voltage must decrease. As clock rates rise and more function is integrated into micro processors (Ps) and application specific integrated circuits (ASICs), the power consumed must increase. These trends are summarized for the 1990s in table 1. Given the voltage and power consumed, the current is calculated from Ohms law. Assuming that only a small percentage of the power supply voltage (i.e. 5%) is allowed as ripple voltage (noise), a target impedance for the PDS is calculated. The target impedance is falling at an alarming rate, 5X per computer generation1.
Z target = (Power Supply Voltage) x (allowed ripple) (5V)x(5%) = = 0.250 Ohms current 1 amp

year

voltage (volts) -------------5.0 3.3 2.5 1.8 1.2

-------------1990 1993 1996 1999 2002

power dispated (watts) -------------5 10 30 90 180

current (amps) -------------1 3 12 50 150

Ztarget (mohms) -------------250 54 10 1.8 0.4

frequency (MHz) -------------16 66 200 600 1200

Table1: target impedance is droping by a factor of 5 every computer generation.

The target impedance must be met not only at DC, but at all frequencies where current transients exist2. The target impedance must be met in the kHz range because the P may be processing code for 0.5 mSec, then require some information from a hard drive and have little activity for 0.5 mSec and repeat the process over and over again. It must be met in the MHz range because the P may require something from DRAM memory, work for a while, and then require something else. And, it must be met near the clock frequency because the P demands and ceases to demand current on that time scale. The PDS must be designed to handle all possible current transients. This essentially means that the PDS must be no more than about twice the target impedance over a broad frequency range (current transients are commonly about half of the maximum current). Figure 1 shows the target impedance vs. frequency for a modern CMOS computer system. Several major components are used to meet this target impedance over the frequency range. The voltage regulator module (VRM) is effective up to about 1 kHz. Bulk capacitors supply current and maintain a low PDS impedance from 1 kHz to 1 MHz. High frequency ceramic capacitors maintain the PDS impedance from 1 MHz to several hundred MHz. The interplane capacitance and the impedance of the printed circuit board power planes are important above 100 MHz. This paper will discuss design considerations for the VRM, bulk capacitors and high frequency ceramic capacitors. If Moores Law and CMOS scaling is to continue, the PDS design will be an increasingly difficult design problem.
impedance

1999 Target Impedance

2 mOhm

1 Hz
switching power supply

1 kHz

1 MHz

1 GHz

frequency

electrolytic bulk capacitors

ceramic high frequency capacitors

PCB power planes

+
+ _

LPF

Vdd
Gnd

Vref

Figure 1: A flat power supply impedance vs. frequency is met by using VRM, bulk capacitor, high frequency ceramic capacitor and power plane components.

Voltage Regulator Module

The Voltage Regulator Module (VRM) converts one DC voltage to another, for example 5V to 1.8 V. It has a reference voltage and a feedback loop. It senses the voltage near the load and adjusts the output current to regulate the voltage at the load. The bandwidth of the regulation loop is usually between 1 kHz and several hundred kHz. At frequencies above the loop bandwidth, the VRM becomes high impedance.

L1 S1
+ _

L_out

R0

C1 S2
A

load
+ _

reference voltage (a) R_flat L_slew

+ _

ESR

L_out

R0 load

(b)

Figure 2: a) simplified block diagram of buck switching regulator and b) linear model for VRM.

Figure 2a is a simplified block diagram for a buck switching regulator, commonly found in VRMs. At the left of the diagram is an input voltage, assumed to be relatively constant. The function of inductor L1 is to store up energy when switch S1 is closed, and deliver current to the load. If L1 has more current than the load is demanding, S1 opens and S2 closes. Current continues to flow to the load, but in an ever diminishing amount until S2 opens and S1 closes again. There is an amplifier A with frequency compensation that senses the load voltage with respect to a reference voltage. When the load voltage is too low, it causes the switches and inductor to ramp up the current. When the load voltage is too high, it causes the switches and inductor to ramp down the current. The inductor current is integrated in C1, which smooths out the voltage. C1 has an equivalent series resistance (ESR). The buck regulator is nonlinear because switches open and closed as a function of time. In the architecture design phase for the PDS, it is highly desirable to have a linear model for the VRM. Figure 2b shows such a model consisting of an ideal voltage source and four passive elements. Spice analysis of this model runs very fast in both the frequency and time domains. It is sufficiently accurate to estimate the amount of bulk capacitance necessary for the PDS. Many of the components are common to both the nonlinear and linear model. R0 is the value of the resistor between the VRM sense point and the actual load and is usually only a few mOhms. A VRM is not capable of regulating the voltage at the actual load. One square of copper for a pair of power planes is about 1 mOhm. L_out represents the output inductance of the VRM. It may be the inductance of cables that connect the VRM to a system board or it may be the inductance of pins that connect a VRM to a P module (about 200 nH and 4 nH respectively). The maximum effective frequency for the VRM is determined by L_out. R_flat represents the ESR of the capacitor associated with the VRM. Generally, the capacitor will determine the output impedance of the VRM at frequencies beyond the response time of the loop. The ideal voltage source has the value of the power supply voltage.

L_slew is the only element in the linear model that is not traceable back to an element in the nonlinear VRM model. The value of L_slew is chosen so that current will be ramped up in the linear model in about the same time that it is ramped up in a real VRM. It is calculated from the equation: V = L di/dt. V is the amount of voltage droop or spike that can be accepted on the PDS (i.e. 5% of 1.8V). The maximum transient current is used for di. The total amount of time for the VRM to ramp this transient current either up or down is used for dt. A sample calculation for L_slew for a VRM that can ramp down 20 amps in 15 uSec is: L_slew = V dt 15uSec = (1.8V* 0.05) = 67.5nH di 20A

parameter R0 L_out R_flat L_Slew 1 4 30 67.5

value nH

units mOhm mOhms nH

Table 2: Typical parameter values for a VRM.

Table 1 gives typical parameter values for a VRM. In this case, the VRM is a small PCB attached to a processor module by a pair of large copper pins. Fig 3a shows the output Impedance vs. frequency of the VRM using these parameters. One amp is forced into the output terminals of the VRM. The voltage is measured and interpreted as ohms. The values of R0 and R_flat are readily seen on the diagram. Fig 3b shows the time domain response of this VRM to 20 amp transients occurring at 10 kHz with a 1 uSec rise time. The nominal power supply voltage was 2 Volts. The voltage measured at the load is slightly below that because of the R0 resistance. Current transients are drawn from the PDS by using a time dependant resistor. The current waveform is shown in figure 3c. The PDS exceeds the +-5% specification limit for several Sec. This may be more than 1000 clock cycles for a modern P.

Figure 3 a) output impedance vs frequency of typical VRM, b) time response of VRM to current transient, c) 20 amp, 50 uSec current pulse with 1 uSec rise and fall times.

Bulk Capacitance
Bulk decoupling capacitors are necessary to maintain the PDS impedance at frequencies above those maintained by the VRM and below the frequencies where ceramic capacitors are effective. There must be sufficient capacitance in the PDS to supply the current and support voltage until the VRM can respond. That amount of capacitance is calculated from the equation I = C dv/dt. Suppose there is a 20 amp current transient, the VRM responds in 15 uSec, and the PDS must remain within 5% of a 1.8V power supply. The amount of bulk capacitance required is estimated by hand calculations:

C= I

dt 15 uSec = 20A * = 3333 uF dv 1.8 V* 0.05

This may over estimate the required bulk capacitance by a factor of 2 because the VRM is ramping up current and the average current may be half of the final value during the VRM response time. But, more capacitors may be necessary if the ESR of the bulk capacitors in parallel is higher than the target impedance. The idea is to keep the PDS below some target impedance through the transition from VRM frequencies to bulk capacitor frequencies. The performance of a VRM is somewhat determined by the loading effects of the bulk capacitance. After estimating bulk capacitance by this method, a cycle-bycycle simulation is necessary with a detailed VRM model fine tune the combined performance of the VRM with the capacitance.

Figure 4: impedance of bulk capacitors vs. frequency.

Bulk capacitors are modeled using series resistance, inductance and capacitance (RLC) elements. Capacitance gives a slope of -20 dB per decade on a log/log impedance vs. frequency (Bode) plot. Resistance gives a flat response with frequency, and inductance gives a +20 dB per decade slope. Spice impedance vs. frequency results for several bulk decoupling capacitors are shown in figure 4. The capacitive, resistive and inductive portions of these curves are readily identified. Capacitors in parallel behave the same as resistors in parallel. The impedance is cut by by the second capacitor, 1/3 by the next capacitor, by the next, etc. Spice simulation is used to determine the impedance of several parallel capacitors and determine the frequency range that is below the target impedance. The transition from VRM to bulk frequencies is observed when bulk capacitors are in the same analysis as a VRM . A properly designed PDS has an impedance that does not exceed the target impedance in the transition from VRM to bulk frequencies.

Figure 5a shows the output impedance vs. frequency when a VRM is placed in parallel with 5 x 2700 uF electrolytic bulk capacitors. The bulk capacitors provide low impedance from VRM frequencies up to almost 1 MHz. Figure 5b shows a spice transient analysis on the same components. The PDS is loaded with 20 amps of current at 100 kHz with a rise time of 200 nSec as shown in figure 5c.

Figure 5a) output impedance vs. frequency of VRM and several bulk capacitors, b) time response of same PDS to current transient, c) 20 amp current transients at 100 kHz with 200 nSec rise and fall times.

High Frequency Ceramic Capacitance

High frequency ceramic capacitors are an increasingly important part of the PDS. Calculations for the number of capacitors necessary to maintain a target impedance are made in the frequency domain3. Ceramic capacitors come in several dielectric types (NPO, X7R, X5R and Y5V) and several sizes (1206, 805, 603). NPO capacitors have the lowest ESR and best temperature and voltage properties, but are only available up to a few nF. X7R capacitors have reasonable voltage and temperature coefficients and are available from several nF to several uF. X5R is similar to X7R, but with reduced reliability and are being extended to 100 uF. Y5V dielectric is used to achieve high capacitance values, but has very poor

voltage and temperature characteristics. Interesting thin film capacitor solutions are also becoming available4.

Series RLC
A reasonable model for a ceramic capacitor is a resistance, inductance and capacitance (RLC) series circuit. Figure 6a shows impedance vs. frequency for capacitors 1 and 2, which are described in table 3:
cap 1 10 nF 100 mOhm 5 nH cap 2 1 nF 100 mOhm 5 nH cap 3 1 nF 100 mOhm 0.5 nH

Table 3: Capacitor values analyzed in figure 6.

The impedance profile for each capacitor comes down on two different capacitive lines. It bottoms out at the equivalent series resistance (ESR), then goes up on the line associated with the inductance. Capacitor 2 is said to have a higher Q because it is more peaked at the resonant frequency. Notice that the impedance at resonance of cap 2 is less than might have been expected if the 1/jc capacitive line had continued. That is because the capacitive portion of the capacitor is in resonance with the inductive portion. Resonance occurs at the frequency: 1 f0 = 2 LC Figure 6b shows impedance vs. frequency for capacitor 2 and Capacitor 3 which has less inductance. Once again, the ESR determines the depth of the curves. But notice that the impedance minimum for the less inductive capacitor is at much higher frequency. In fact the impedance is reduced at all higher frequencies because of the low inductance. The effectiveness of high frequency decoupling capacitors is greatly increased when the inductance is minimized.

Figure 6: Simulation of RLC capcitor models with a) different capacitance values and b) differenet inductance values.

ESR
An HP4291 is used to measure capacitor ESR by soldering it to an SMA connector and attaching it to a test head through an APC-7 connector. Measurements using a traditional surface mount test head may underestimate the actual ESR5. ESR and contact resistance are hard to separate and a portion of the ESR may be lost during the compensation process. Figure 7 summarizes the ESR measured on capacitors from several different vendors. ESR is a strong function of dielectric type. Below 1 nF, it would take many X7R capacitors in parallel to achieve the impedance of a single NPO capacitor.
ESR for capacitors
2000

1500

miliOhms

1000

X7R
500

NPO

10

100

1000

pF 10000

100000

1000000

Figure 7: ESR vs capacitor value for NPO and X7R capacitors, 805 and 603 size.

Inductance
Inductance is the amount of energy stored as magnetic flux (B field) in the environment as a result of current. A well known way to make an inductor is by a coil of wire or a loop, where flux is concentrated in the center. A good way to make the loop less inductive is to minimize the loop area. This holds true for decoupling capacitors. Figure 8 shows how current travels in a loop when it leaves a power plane, travels through a via, pad structure, discrete decoupling capacitor, via, and returns to a ground plane. The inductance of the current loop is minimized by bringing the vias close together and reducing the height of the vias and capacitor.

Capacitor

Capacitor
Vias Pad

x x x

Vdd Gnd

Vias

Pad Vdd Gnd

B Fields

Figure 8: The inductance of a capacitor is mostly in the pad and via structure. Inductance is minimized by minimizing the area of the current loop.

Figure 9 shows progress in decoupling capacitor pad design. In the early 1990s, decoupling capacitor inductance was dominated by pad layout. A small trace between the pads and vias adds an enormous amount of inductance. Vias should be brought as close together as possible to minimize inductance. The limiting factors are manufacturing issues at PCB fabrication and component assembly.
l
Earlier design 4 95 design

Pad Inductance
l
96 design

Pad Trace, via

nanoHenry

3 97 design

2 current design future design 1

Figure 9: Decoupling capacitor pad design progression. Pad layout is a major contributor to capacitor inductance.

With optimum pad design, the dominant inductance is associated with the via and capacitor height. The vertical distance traversed by the current increases the size of the loop and therefor the inductance. The effect of capacitor height is shown in figure 10. By optimizing the pad design and minimizing the distance from the top of the capacitor to the power/Gnd plane pair, the inductance associated with decoupling capacitors is minimized.

Capacitor height

Thickness(mils) Inductance(pH) 20 300 30 450 40 600 50 700

Figure 10: Height adds inductance to the capacitor.

Parallel Capacitors
To achieve low PDS impedance, many capacitors are placed in parallel. Figure 11 shows the effect of placing several identical capacitors in parallel. The impedance is reduced by a factor of 2 every time the number of capacitors is doubled. There is a diminishing return with each additional capacitor. It is desirable to start with low ESR capacitors in order to minimize the number of capacitors required to meet a target impedance.

Figure 11: identical capacitors in parallel. The impedance is reduced by a factor of two every time the quantity is doubled.

Capacitors of different values in parallel produce an unwanted anti-resonance. A peaking between the two minimums of two capacitor values is shown in figure 12. The peak is higher than the impedance of either capacitor by itself. The peak is associated with the circuit that is formed after one capacitor has gone inductive and the other capacitor is still capacitive, the classic parallel LC tank circuit. The most effective way to reduce the height of the anti-resonance is to minimize inductance. Figure 12b shows the same set of capacitors mounted on low inductance pads. Notice that the peak is much lower compared to a target impedance. Large anti-resonant peaks develop when low ESR capacitors are placed on inductive pads. High inductance and low resistance make a high Q circuit, Q = L/R. NPO capacitors have low ESR and should always be used on low inductance pads. The anti-resonance also becomes high if large gaps exist in capacitance value. Figure 12c shows the same quantity of capacitors as 12a and 12b, but they have been distributed over 3 values instead of 2. The PDS impedance is below target over a broad frequency range. Anti-resonances are effectively managed by using low inductance pad structures and many values of capacitors.

Figure 12: Anti-resonance of parallel capacitors with a) inductive pads, b) low inductance pads, and c) with a third value of capacitor but the same quantity. Note that multiple values of capacitors on low inductance pads keeps the PDS below the target impedance for a broader frequency.

Ceramic Capacitor Methodology

Figure 13 shows the impedance vs. frequency for several X7R and NPO ceramic decoupling capacitors. Notice that as the capacitance value decreases and the resonant frequency goes up, the impedance minimum does not dip down as low. ESR is lower for high valued capacitors. A methodology has been developed for meeting aggressively low target impedances at high frequency. Capacitors are placed in parallel until their parallel impedance meets the target impedance. Advantage is taken of resonance where ESR is lower than the impedance that can be reached by either the capacitive or inductive curve for that capacitor. This is key in minimizing the number of capacitors necessary to keep a PDS below a target impedance. At high frequencies it becomes difficult to put enough capacitors in parallel to reach a target impedance. Capacitor effectiveness is optimized by using low inductance pads to increase the resonant frequency of a given capacitor.

Figure 13: Impedance vs. frequency for several X7R and NPO capacitors.

Figure 14 shows the characteristics of a PDS including the VRM, 7 bulk capacitors, and 115 ceramic capacitors. The capacitors were chosen to keep the PDS below the target impedance until nearly 200 MHz as shown on the frequency plot. The PDS has been stimulated with 20 Amp, 50 MHz current transients that have a rise time of 2 nSec. The time domain response of the PDS shows that the voltage stays almost within 5% of the nominal Vdd, in spite of the very harsh transients. There is some energy above 200 MHz that is causing spikes to drop below the limit. Those spikes are dealt with most easily with power plane capacitance6.

Figure 14: a) Impedance vs. frequency of PDS with VRM, bulk and 115 ceramic capcitors, b) time domain responce of same PDS to current transients, c) 50 MHz current transients with 2 nSec rise times.

Conclusions
Modern CMOS technology requires a low impedance power distribution system across a broad frequency range. The major components in this system include the voltage regulator module, bulk capacitors and high frequency ceramic capacitors. The impedance vs frequency of each of these components have been discussed and modeled in spice. A methodology for choosing the values and quantities of these components has been defined. The methodology involves placing a sufficient quantity of components in parallel to meet the target impedance in the frequency domain. Examples of frequency domain and time domain analysis has been given. If the target impedance is met in the frequency domain, noise in the time domain stays below a specified amount. Power distribution systems are efficiently designed using this methodology.

_________________________ 1 L.D.Smith, "Packaging and Power Distribution Design Considerations for a Sun Micosystems Desktop Workstation," Electrical Performance of Electrical Packages Conference, Oct, 1997. 2 Wiren D. Becker et al., "Modeling, Simulation and Measurement of Mid-Frequency Simultaneous Switch Noise in Computer Systems," IEEE Transactions on Components, Packaging and Manufacturing Technology - Part B, Vol. 21, No. 2, May 1998. 3 L.D.Smith, "Decoupling Capacitor Calculations for CMOS Circuits," Electrical Performance of Electrical Packages Conference, Nov, 1994. 4 K.Y. Chen, W.D. Brown, and L.W. Schaper, "Modeling and Simulation of Thin Film Decoupling Capacitors," Electrical Performance of Electrical Packages Conference, Oct 1998. 5 Tanmoy Roy, Larry Smith, John Prymak, "ESR and ESL of Ceramic Capacitor Applied to Decoupling Applications," Electrical Performance of Electrical Packages Conference, Oct 1998. 6 Larry D Smith, Raymond Anderson, Doug Forehand, Neilus OSullivan, Tanmoy Roy, "Power Plane analysis for CMOS Power Distribution Systems," work to be published.