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    Design of Upsampler

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    prasu440
    The document describes the design of an upsampler and CIC filter in Verilog. It includes: 1) Design objectives to develop Verilog code for an upsampler and CIC filter, perform verification with test cases, and synthesis. 2) Description of upsampler and interpolation design including inserting zeros to increase sampling rate. 3) Implementation of the upsampler in Verilog including use of counters and assigning output. 4) Design of the CIC decimator and interpolator including integrator, comb, and down/upsampling sections.

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    Design of Upsampler

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    prasu440
    502 views7 pages
    The document describes the design of an upsampler and CIC filter in Verilog. It includes: 1) Design objectives to develop Verilog code for an upsampler and CIC filter, perform verification with test cases, and synthesis. 2) Description of upsampler and interpolation design including inserting zeros to increase sampling rate. 3) Implementation of the upsampler in Verilog including use of counters and assigning output. 4) Design of the CIC decimator and interpolator including integrator, comb, and down/upsampling sections.

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    The document describes the design of an upsampler and CIC filter in Verilog. It includes: 1) Design objectives to develop Verilog code for an upsampler and CIC filter, perform verification with test cases, and synthesis. 2) Description of upsampler and interpolation design including inserting zeros to increase sampling rate. 3) Implementation of the upsampler in Verilog including use of counters and assigning output. 4) Design of the CIC decimator and interpolator including integrator, comb, and down/upsampling sections.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    502 views7 pages

    Design of Upsampler

    Uploaded by

    prasu440
    The document describes the design of an upsampler and CIC filter in Verilog. It includes: 1) Design objectives to develop Verilog code for an upsampler and CIC filter, perform verification with test cases, and synthesis. 2) Description of upsampler and interpolation design including inserting zeros to increase sampling rate. 3) Implementation of the upsampler in Verilog including use of counters and assigning output. 4) Design of the CIC decimator and interpolator including integrator, comb, and down/upsampling sections.

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    At a glance
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    The key takeaways are that upsamplers increase the sampling rate of a signal by inserting zeros, CIC filters can operate as both interpolators and decimators, and the integrator and comb sections perform accumulation and subtraction operations respectively.

    The main components of an upsampler are a counter to track the sampling factor and insert zeros, and logic to pass the input sample when the counter equals 1 and pass zeros otherwise.

    The main components of a CIC filter when used as an interpolator are a comb section, an upsampler, and an integrate section.

    CHAPTER DESIGN OF UPSAMPLER AND APPLICATION CIC INTERPOLATOR

    Design Objective: The following are the design objectives. To design Verilog code for upsampler and write the code in Verilog To design CIC (cascaded Integrated Comb) filter which works as interpolator and decimator when enabled To perform the verification of above modules by writing different test cases in Verilog To perform the synthesis of the design using Xilinx XST simulator

    Design of Upsampler in Verilog

    Upsampler with sampling factor L, where L is a positive integer and every Lth sample is taken from x[n] with all others zero which develops an output sequence xe[n] with a sampling rate that is L times greater than that of the input sequence.

    Fig. 1 Block-diagram representation

    Interpolation: A process of increasing the sampling rate called interpolation. It is a method of constructing new data points within the range of a discrete set of known data points. Interpolation increase sampling rate by integer factor. Interpolation is the exact opposite of decimation. It is an information preserving operation, in that all samples of x[n] are present in the expanded signal y[n]. The mathematical definition of L-fold interpolation is defined. Interpolation works by inserting (L1) zero-valued samples for each input sample. The sampling rate therefore increases from Fs to LFs. Expansion process is followed by a unique digital lowpass filter called an anti-imaging filter. Although the expansion process does not cause aliasing in the interpolated signal, it does however yield undesirable replicas in the signals frequency spectrum. It depicts 3-fold interpolation of the signal x[n] i.e. L = 3. The insertion of zeros

    effectively attenuates the signal by L, so the output of the anti-imaging filter must be multiplied by L, to maintain the same signal magnitude. Implementing Up sampler in Verilog HDL:

    The Verilog code is parameterized. The sampling rate depends upon the parameter factor There are two integers count and count_temp If the start input is asserted then only the counting takes place. And the value of the count gets incremented with respect to the positive edge of the clock input. If the count becomes equivalent to the parameter factor then make the count to a zero.

    Count is assigned to count_temp The upsampler output is dependent on start as well as the count_temp signals; if the start is asserted to 1 and count_temp is a 1 then the output is equivalent to input sample. Hence the sample rate increases here. For one input sample the corresponding output has 3 samples if the factor is 2, the extra samples are zeroes. This can be observed in the expected output waveform graph.

    Expected Output Waveform

    Verilog code: module upsampler #(parameter factor =2) (input [1:0] upsampler_input, input clk, input start, output [1:0] upsampler_output); integer count_temp; integer count = factor; always@(posedge clk) begin

    if(start) begin if(count == factor) begin

    count <= 0; end else begin count <= count + 1; end end count_temp <= count; end

    assign upsampler_output = (start && (count_temp == 1))?upsampler_input:2'b00; endmodule

    DESIGN OF CIC DECIMATOR AND INTERPOLATOR Text substitution macros used: `define C_INTERPOLATING_FILTER 1 `define C_DECIMATING_FILTER 2 Parameters used: parameter C_DATA_WIDTH = 10;

    parameter C_DIFFERENTIAL_DELAY = 1; parameter C_ENABLE_RLOCS parameter C_FILTER_TYPE parameter C_RESULT_WIDTH = 0; = `C_INTERPOLATING_FILTER; = 12;

    parameter C_SAMPLE_RATE_CHANGE = 3; parameter C_STAGES // constants parameter ACCUM_MAX_WIDTH = 64; = 1;

    parameter NUMBER_OF_ACC_STAGES = (C_RESULT_WIDTH+ACCUM_MAX_WIDTH1)/ACCUM_MAX_WIDTH; parameter RESULT_DELAY Decimating Filter: It consists of 1. Integrator 2. Downsampler 3. Comb Interpolating Filter: It consists of = NUMBER_OF_ACC_STAGES*C_STAGES;

    1. Comb section 2. Upsampler 3. Integrate section

    Tasks Integrator: The integrator section consists of C_STAGES cascaded accumulators. The total delay of the integrator section is RESULT_DELAY cycles. If there is a new input to the integrator section (nd is asserted), a new result is calculated, and stored in the result array to be delayed by RESULT_DELAY cycles. The valid array records if a valid value is stored in the corresponding position of the result array. Every clock cycle, the resultptr is updated to check if a result is now available to be output from the integrator section. COMB SECTION The comb section consists of C_STAGES cascaded subtractors. Each subtractor subtracts a delayed input from its current input. The input may be delayed 1 or 2 cycles. The total delay of the comb section is RESULT_DELAY cycles. If there is a new input to the comb section (nd is asserted), a new result is calculated, and stored in the result array to be delayed by RESULT_DELAY cycles. The valid array records if a valid value is stored in the corresponding position of the result array. Every clock cycle, the resultptr is updated to check if a result is now available to be output from the comb section.

    DOWN SAMPLER The first data input (when nd is asserted) is passed to data_out, and rdy is asserted. The next C_SAMPLE_RATE_CHANGE-1 inputs are ignored, and rdy remains deasserted. UP SAMPLER The first data input (when nd is asserted) is passed to data_out and rdy is asserted. For the next C_SAMPLE_RATE_CHANGE-1 cycles, zero is passed to data_out and rdy stays asserted. INTERFACE DIAGRAM

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