Design and Implementation of Automatic Train Ticketing System Using Verilog HDL

Muhammad Ali Qureshi1, Abdul Aziz1, Hafiz Faiz Rasool2

Assistant Professors, 2 Student, Department of Electronic Engineering, University College of Engineering & Technology, The Islamia University of Bahawalpur, Pakistan. [email protected], [email protected], [email protected]

Abstract Automatic Train Ticketing System (ATTS) dispense train tickets at railway stations in the absence of salespersons. ATTS has been implemented in many countries as the number of passengers increases day by day, but not yet in Pakistan. In Pakistan passengers get a ticket at the counter, it is a time consuming process and create problems if passengers are in hurry during rush hours. So it becomes necessary to implement an automatic train ticketing machine, which contain all destination tickets and easy to use for all passengers for 24 hours. That is why in this paper FPGA based ATTS design and implementation on Spartan-3 xc3s400 is proposed, because FPGA based ATTSs has many advantages over existing microcontroller based ATTSs, some of these advantages are; simple structure high reliability, speed, number of input/output ports, performance and less power consumption which are all very important in every ATTS design. This system is implemented on the basis of finite state machine (FSM), by using Xilinx State CAD tool. This machine accepts coins in any sequence, and deliver tickets when the desired amount is deposited, it also give back the change if inserted amount is greater than the required amount, it also has a cancel option if a passenger wants to get his money back before the ticket out he/she will use the cancel option. This system can be extended in future without changing any hardware, just by reprogramming the system it can be enhanced for multiple stations.

cash card or credit cards. One of the greatest selling point of a vending machine is its availability to the customers at all time of the day.[8] The existing FPGA based ATTSs are based on handwritten programming ,it is a time consuming process for programmer, if hardware designer wants to enhance the features of FPGA based ATTS, he will write a new program, and he will get the results after facing lot of steps and errors in new handwritten program. The design of proposed FPGA based ATTS is based on Xilinx State CAD tool, this allows for designer to simply change the state diagram of existing system for increment in features of that system, in very short time the programming file automatically generated by the state CAD tool. The system will start process after a very short time interval. Some current available systems used in such applications are given below that are mostly used by United Kingdom, Germany, China and British Train Operating Companies (TOCs).

Keywords- FSM, FPGA, StateCAD, Verilog HDL, Xilinx. I. INTRODUCTION

Vending machines have been in existence as early as 1880s, the first commercial coin-operated vending machines were introduced in London, England selling post cards. The first vending machine in the U.S. was built in 1888 by the Thomas Adams Gum Company, selling gum on train platforms. [8] In our present days, vending machines can be found everywhere in our everyday life. For example, vending machine can be found at the train stations selling train tickets. In the schools and offices vending can drinks and snacks. The mode of trading also changes from the coins and notes system to cashless transaction with the introduction of
Figure 1. Train ticketing machine installed at British railway station

Ascom B8050, usually known by the name Quickfare, is an early example of a passenger-operated railway ticket issuing system, consisting of a series of broadly identical machines installed at British railway stations from 1989

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onwards. The machines allow passengers to buy the most popular types of ticket themselves, without having to go to a booking office, and are therefore useful at unstaffed, partly staffed or busy stations. Almost all Quickfare machines have been replaced by more modern technology ATTSs[14]. The ShereFASTticket system is also a passengeroperated, self-service railway ticket issuing system, developed by the Guildford-based company Shere Ltd and first introduced on a trial basis in Britain in 1996, shortly after privatisation. It has been developed and upgraded consistently since then, and is now used by seven Train Operating Companies (TOCs) as their primary self-service ticket issuing system. Other TOCs have FASTticket machines at some of their stations, sometimes supplementing other systems[10]. The Avantix B8070, more commonly known as Avantix MultiTicket was a passenger-operated railway ticket issuing system, installed at British railway stations from 1999 onwards. The machines were available as upgrades to the Ascom B8050 Quickfare or as new build. The machine was developed by Sema Group, later SchlumbergerSema and then Origin. Most machines were withdrawn during 2007 and 2008. The last Avantix B8070 was withdrawn in January 2009 due to limitations and replaced by modern machines[15]. The Scheidt & Bachmann Ticket XPress system is a passenger-operated, self-service railway ticket issuing system developed and manufactured by the German systems development and production group.It uses Intel Atom N270 microprocessor[11]. The Ascom EasyTicket is a railway ticket issuing system used in Britain, consisting of a series of self-service (passenger-operated) machines at railway stations. Having been introduced in 2003 by several Train Operating Companies (TOCs)[13]. Add-Value Machine is also a railway ticketing machine used in Hong Kong made by KML technology limited Hong Kong[12]. The above conventional ATTSs are based on microcontroller based technology, they have inflexible infrastructure , slow speed and some time they need exact amount , and some systems do not have the cancel options if passenger wants to get his money back during the process, also the above systems dont have the reprogramming ability. Choosing the correct devices for the heart of any system is very difficult and is made even harder by the emergence of new technologies. In modern technologies such as Field Programmable Gate Arrays (FPGA) is the best technology to meet above system requirements[1]. Custom processor based ATTSs have inflexible architectures and the inflexibility of these systems prevents

upgrading products to meet changing market needs, while FPGA based ATTSs are flexible and can be reprogrammed and redeployed as needed, using FPGA based systems instead of custom devices means no risk of obsolete inventory because standard product FPGA can be redeployed to different applications as needed. Unlike custom processor, FPGA chip do not have to be scrapped if a specific project is canceled[1,7]. Custom processor based ATTSs are also slow speed because they have serial processing that limits data throughput, while in FPGA parallel processing maximizes throughput, as FPGA architecture consists of a lot of memory blocks referred to as look-up-tables(LUTs),which can be utilized to improve performance of certain operations such as multiplication while the speed can be tolerated, that is why FPGA gives fast response than the microcontroller based systems[2,7]. ATTSs using Custom processors can face the need for board redesigning during upgrading while FPGA reprogram ability avoid this problem simply by downloading a new hardware configuration file to the FPGA without changing any hardware[1,9]. FPGA has the ability to embed multiple processors in a single FPGA, this ability reduce the size and cost of any FPGA based system[1,8]. A. Finite State Machine The proposed system is based on finite state machine (FSM). FSM is a digital sequential circuit that consists on number of pre-defined states that are controlled by one or more inputs[4]. The FSM remain stable until the inputs changes. There are two types of finite state machines: Synchronous and Asynchronous FSMs. Synchronous FSMs have a clock input and are also called Mealy machines, while asynchronous FSMs are without clock input and are called Moore machines[5].The given system is also based on Mealy machine model. B. Xilinx StateCAD tool In this paper Xilinx State CAD tool is used to implement the ATTS design. It usually describe the behavior of sequential machine by defining outputs, inputs, and transitions between states. When the diagram is complete the software translates the visual representation into a Hardware Description Language (HDL). It is not necessary to understand the language. The use of State CAD tool is not too difficult, and there is no need to understand how to translate from a state diagram into useable sequential logic. State CAD does everything. After the HDL has been generated, it can be added to the project as a source file and turned into a schematic symbol. State Bench is used to view the result waveforms and finally generated HDL file is downloaded to the FPGA board for verification of the design[6].

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II.

IMPLEMENTATION

The FPGA design flow for the ATTS system is as follows. First, The logic of the system is developed in the form of state diagram with the help of Xilinx StateCAD tool, and simulated at the register transfer level (RTL) to verify the correctness, the placement and routing are carried out automatically to generate the FPGA implementation le. Finally, the generated implementation le is downloaded to the FPGA development board for testing of the design[7,8]. This system supports for four railway stations ,namely Lahore ,Multan, Karachi and Bahawalpur .The system can accepts the coins in any sequence. The list of used stations with fares is given in TABLE II.There are four destinations selection buttons, namely SEL_LAHORE, SEL_MULTAN, SEL_BWP and SEL_KARACHI. If a passenger wants to go to Lahore he/she push the button SEL_LAHORE. There are three coins will be used in our proposed system these coins are COIN1, COIN2 and COIN3, and have the values of one rupee ,two rupees and five rupees respectively. Also a CANCEL button is used if the passenger wants to get his money back before the ticket out at any stage. The outputs are CHANGE, COIN_SUM, RETRN and TICKET. Here COIN_SUM is an internal vector while CHANGE and RETRN are output vectors. The four bit bus or vector variable COIN_SUM counts the amount of money inserted at every transition. CHANGE and RETRN are also four bit wide vectors. These two output vectors are used to display the change and the amount of money that has been returned to the user if he/she push CANCEL button. The system changes its states on every transitions of positive edge of clock cycle represented by input CLK. The system returns to its initial state when RESET is asserted. The detail list of input and output ports are shown in TableIII. After synthesizing the HDL file, Register Transfer Level (RTL) schematic diagram is shown in Figure2 and the synthesis report is shown in Table I.

Figure 2. TABLE II.

RTL Schematic Diagram

No.
1 2 3 4

Selected stations
Lahore Multan Bahawalpur Karachi

Fares
Rs.6/Rs.7/Rs.8/Rs.9/-

TABLE III.

PORTS DESCRIPTION

Port Name
CLK RESET CANCEL COIN1 COIN2 COIN3

Direction
Input Input Input Input Input Input Input Input Input Input Output Output Output Output

Width
1 1 1 1 1 1 1 1 1 1 1 4 4 4

Remarks
Clock Synchronous Reset Cancel One Rupee Two Rupees Five Rupees Lahore Railway station Multan Railway station Bahawalpur Rlwy stn Karachi Railway station Selected Stn Ticket Out Extra Money Sum of inserted coins Return money if cancel

TABLE I.

DEVICE UTILIZATION SUMMARY

SEL_ LAHORE SEL_MULTAN

Logic Utilization
Number Of Slices Number of Slice Flip Flops Number of 4 input LUTs Number of bonded IOBs Number of GCLKs

Used
135 50 229 29 1

Available
768 1536 1536 124 8

Utilization
17% 3% 14% 23% 12%

SEL_BWP SEL_KARACHI TICKET CHANGE COIN_SUM RETRN

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III.

STATE DIAGRAM DESCRIPTION

First of all, reset the system by pushing RESET button, its mean the system is ready for use to select desired railway station and this state is represented by initial state (INIT) in the State diagram. You can see that in the state diagram at every transition there is a condition so that the system can decide which is the next state to be executed. When the passenger will insert a coin, the system will check the condition at every transition. After executing the correct condition, the system will come back to the WAITING state. After putting coins in any sequence the passenger will get the required selected station ticket, if the coin sum is equal or greater than the selected railway station then the system will release the ticket out. In this paper, for four railway stations and three coins there are twenty six states, the complete state diagram is shown in Figure 3. Suppose a passenger wants to go to Lahore then he will push the SEL_LAHORE button as a result the system will enter into the WAITING_1 state from INIT state. At this WAITING_1 state the system will wait for coins, suppose the passenger inserts a COIN2, then the system will enter into the STATE_2, which shows that two rupees has been deposited and system will shows COIN_SUM equal to two. At STATE_2 the value of TICKET and CHANGE is zero. The system will comeback automatically to the WAITING_1 state and it will wait for more coins of any value. Suppose the passenger inserts the COIN3, the system will go to STATE_3 at this state the value of COIN_SUM will be seven rupees. Again the system will come back to the WAITING_1 state at which the output condition is checked. As the condition(COIN_SUM>6) is correct therefore the system will enter to the LAHORE_TICKET_OUT state and the ticket of Lahore station will released as the COIN_SUM is seven rupees which is greater than the selected station fare so the system will give the change of one rupee with the ticket. If he/she presses the CANCEL button then he/she will get his money back. Similarly the passengers can select all the other stations by following the same procedure. IV. SIMULATION RESULTS

Suppose he/she inserts two coins of two Rupees and suddenly he/she changes his mind to get ticket for another station then he/she has a option to get his/her money back simply by pressing a Cancel button. The same procedure is adopted in Figure 6. V. CONCLUSION

The existing FPGA based ATTSs are based on handwritten programming, in this way hardware designer get the results after a lot of steps and errors that are faced in writing the HDL code directly. The design of proposed FPGA based ATTS is implemented using finite state machines with the help of Xilinx StateCAD tool, this allows designing the model without cumbersome, text oriented and error prone rules. Hardware designer can capture their ideas as a state diagram without the handwritten documentation. The proposed ATTS can be verified simply by changing the state diagram. This is a time saving method for engineers, State machines based ATTS enhances productivity, reduces system development cost, and accelerates time to market. ACKNOWLEDGMENT We wish to thank all our respected teachers and friends for their excellent contributions and support for the completion of this paper. Specially we are very much thankful to Dr. Muhammad Mukhtar the Vice Chancellor of the university, and Professor Jan Muhammad Keerio the Principal of UCET, for their efforts to facilitate and provide us most suitable environment for research and development. REFERENCES
[1] Karen Parnell, Roger Bryner., Comparing and Contrasting FPGA and Microprocessor System Design and Development, Xilinx Inc, 21 July, 2004. Xilinx Inc., Spartan 3 Data sheet: http://ww w.xilinx.com. Pong P. Chu, FPGA Prototyping using Verilog HDL-Xilinx Spartan-3 Version, John Wiley & Sons, 2008. Peter Minns, Ian Elliott, FSM-based Digital Design usingverilog HDL, John Wiley & Sons, Ltd 2008. Samir Plantikar, Verilog HDL, 2nd Edition, Prantice Hall, 2003. http://www.cs.unipa.it/old/corsi/architetturei/MaterialeStudenti/VH DL/StateCAD.pdf Michael D.ciletti, Modeling, synthesis and Rapid prototyping with verilog HDL,Prentice Hall,1999. http://inventors.about.com/od/uvstartinventions/a/vending.htm Steve Kilts, Advanced FPGA Design :Architecture, Implementation, and optimization ,Wiley-IEEE press,2007. http://www.shere.com/products/services/railticket/vendingmachines http://www.scheidt-bachmann.com http://www.kml.com.hk/download/KML%20SAV%20PDS%20Issu e%201%2012.2006.pdf http://www.enotes.com/topic/Ascom_EasyTicket http://www.stannsulyn.dsl.pipex.com/machines/ascom.pdf http://en.vionto.com/show/me/Avantix+B8070

[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]

The design is simulated using Xilinx stateCAD tool. For different stations and various combinations of coins, the simulated results are shown in Figure 4, 5 and 6 respectively. In Figure 4, the passenger selects the Lahore station. As the Lahore station fare is six rupees, the passenger inserted two coins first COIN1 and second time he/she inserted a COIN3, now the COIN_SUM is seven rupees which is greater than the selected station fare so the system will give the change of one rupee with the ticket. Figure 5 verifies the simulated results for Multan station its fare is seven rupees so the system released the ticket out without any change.

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Figure 3.

State Diagram

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Figure 4.

Selection of Lahore Railway Station

Figure 5.

Selection of Multan Railway Station

Figure 6.

Waveform when Cancel Button is pressed

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