Lecture 25 Vlsi

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EE130 Lecture 25, Slide 1 Spring 2003


Lecture #25
Design Project:
Due in class (5 PM) on Thursday May 1
st
20 pt penalty for late submissions, accepted until 5 PM
on 5/8
Your BJT design does not need to meet the
performance specifications when W
B
and N
B
are varied
by +/- 10%
Equation for E
G
assumes N
E
is in cm
-3
and T is in K
Quiz#5 Results:
(undergrad.s only)
N=60
Mean=20.5
Std.Dev.=3.6
EE130 QUIZ SCORE TREND
21.6
17.9
18.9
17.9
20.5
0
10
20
30
Q1 Q2 Q3 Q4 Q5
EE130 Lecture 25, Slide 2 Spring 2003
OUTLINE
NMOSFET I-V
Effective mobility
Transconductance
PMOSFET I-V
Subthreshold current
2
EE130 Lecture 25, Slide 3 Spring 2003
Ideal MOSFET I-V Characteristics
Linear
region
Saturation
region
(Enhancement Mode NMOS Transistor)
EE130 Lecture 25, Slide 4 Spring 2003
Review: Qualitative Operation of the NMOSFET
depletion layer
The potential barrier to electron flow from the source
into the channel is lowered by applying V
GS
> V
T
Electrons flow from the
source to the drain by drift,
when V
DS
>0. (I
DS
> 0.)
The channel potential
varies from V
S
at the
source end to V
D
at the
drain end.
(The inversion layer can be
modeled as a resistor.)
3
EE130 Lecture 25, Slide 5 Spring 2003
When V
D
is increased to be equal to
V
G
-V
T
, the inversion-layer charge
density at the drain end of the
channel equals zero, i.e. the
channel becomes pinched off
As V
D
is increased above V
G
-V
T
, the
length L of the pinch-off region
increases. The voltage applied
across the inversion layer is always
V
Dsat
=V
GS
-V
T
, and so the current
saturates:
If L is significant compared to L, then
I
DS
will increase slightly with increasing
V
DS
>V
Dsat
, due to channel-length
modulation
Dsat DS
V V
DS Dsat
I I
=
=
EE130 Lecture 25, Slide 6 Spring 2003
NMOSFET I-V Characteristics
V
D
> V
S
Current in the channel flows by drift
Channel voltage V
C
(y) varies continuously between
the source and the drain
Channel inversion charge
(

=
oxe
dep
B C FB G oxe inv
C
y Q
y V V V C y Q
) (
2 ) ( ) (
ox
CB B Si A
B C FB T
C
y V qN
y V V V
)) ( 2 ( 2
2 ) (
+
+ + + =

W
4
EE130 Lecture 25, Slide 7 Spring 2003
1
st
-Order Approximation
Neglect variation of Q
dep
with y
where V
T
= threshold voltage at the source end:
[ ]
C S T G oxe inv
SB B Si A dep
V V V V C Q
V qN Q
+ =
+ =

) 2 ( 2
ox
SB B Si A
B S FB T
C
V qN
V V V
) 2 ( 2
2
+
+ + + =

EE130 Lecture 25, Slide 8 Spring 2003


NMOSFET Current (1
st
-order approx.)
Consider an incremental length dy in the channel.
The voltage drop across this region is
DS
DS
T GS oxe eff DS
V
V
C C inv eff DS
V
V
C C inv eff
L
DS
eff inv
DS
inv eff
DS
inv
DS DS C
V
V
V V C
L
W
I
dV V Q
L
W
I
dV V WQ dy I
W Q
dy I
nWT q
dy
I
WT
dy
I dR I dV
D
S
D
S
(

=
=
=
= = = =


2
) (
) (
0


in the linear region
2
) (
2
T GS eff oxe Dsat DS
V V C
L
W
I I = = in the saturation region
5
EE130 Lecture 25, Slide 9 Spring 2003
Effective Mobility
where
eff
is the effective electron mobility
The NMOSFET can be modelled as a resistor at low V
DS
:
DS T G oxe eff
DS
eff inv eff inv inv DS
V V V C L W
L
V
WQ WQ v WQ I
) ( ) / ( =
|
.
|

\
|
= = =

E
) (
T G oxe eff DS
DS
DS
V V C W
L
I
V
R

= =

EE130 Lecture 25, Slide 10 Spring 2003


Scattering mechanisms:
coulombic scattering
phonon scattering
surface roughness
scattering
(V
gs
+ V
t
+ 0.2)/6T
oxe
(MV/cm)
(V
gs
+ 1.5V
t
0.25)/6T
oxe
(MV/cm)

(NFET)
(PFET)

eff
vs. Effective Normal Field
6
EE130 Lecture 25, Slide 11 Spring 2003
V
T
is a function of V
SB
:
The Body Effect
( )
( )
B SB B T
B SB B
oxe
Si A
T T
V V
V
C
qN
V V

2 2
2 2
2
0
0
+ + =
+ + =
where is the body effect parameter
When the source-body pn junction is reverse-biased, |V
T
|
increases. Usually, we want to minimize so that I
Dsat
|V
GS
V
T
| will be the same for all transistors in a circuit
EE130 Lecture 25, Slide 12 Spring 2003
Problem with the Square Law Theory
Assumes that gate charge is purely balanced by
inversion charge
Ignores variation in depletion width with distance y
7
EE130 Lecture 25, Slide 13 Spring 2003
DS DS T GS eff oxe DS
V V
m
V V C
L
W
I )
2
( =
Modified Model
dm
oxe
oxe
dm
W
T
C
C
m
3
1 1 where + = + =
2
3 since
O Si Si
=
EE130 Lecture 25, Slide 14 Spring 2003
transconductance: g
m
= dI
DS
/dV
GS
2
) (
2
T GS eff oxe Dsat
V V C
mL
W
I =
saturation region:
) (
T GS eff oxe msat
V V C
mL
W
g =
Modified Model: I
Dsat
& Transconductance
m
V V
V V
T GS
Dsat D

=
8
EE130 Lecture 25, Slide 15 Spring 2003
MOSFET V
T
Measurement
V
T
can be determined by plotting I
DS
vs. V
GS
,
using a low value of V
DS
EE130 Lecture 25, Slide 16 Spring 2003
P-Channel MOSFET
The PMOSFET turns on when V
GS
< V
Tp
Holes flow from SOURCE to DRAIN
DRAIN is biased at a lower potential than the SOURCE
In CMOS technology, the threshold voltages
are usually symmetric: V
Tp
= -V
Tn
P
+
P
+
N
GATE
V
S
V
D
V
G
I
DS
V
B
V
DS
< 0
I
DS
< 0
|I
DS
| increases with
|V
GS
- V
Tp
|
|V
DS
| (linear region)
9
EE130 Lecture 25, Slide 17 Spring 2003
DS DS Tp GS eff p oxe DS
V V
m
V V C
L
W
I )
2
(
,
+ =
PMOSFET I-V
Linear region:
Saturation region:
2
,
) (
2
Tp GS eff p oxe Dsat DS
V V C
mL
W
I I = =
m
V V
V
Tp GS
DS

< < 0
m
V V
V
Tp GS
DS

>
m = 1 + (3T
oxe
/W
dm
) is the bulk-charge factor
EE130 Lecture 25, Slide 18 Spring 2003
Sub-Threshold Leakage Current
We had previously assumed
that there is no channel current
when V
GS
< V
T
. This is incorrect.
Consider V
S
close to 2
B
:
There is some inversion charge
at the surface, which gives rise
to subthreshold current flowing
between the source and drain:
) 1 ( ) 1 (
/ / ) (
2
kT qV mkT V V q
oxe eff DS
DS T G
e e
q
kT
m
L
W
C I

|
|
.
|

\
|
=
10
EE130 Lecture 25, Slide 19 Spring 2003
Sub-Threshold Slope S
) 1 )( 10 ( ln
) (log
1
10
oxe
dm
GS
DS
C
C
q
kT
dV
I d
S
+ =
|
|
.
|

\
|

EE130 Lecture 25, Slide 20 Spring 2003


V
T
Design Tradeoff

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