EE707 Advanced Electrical Engineering Lab Manual (2006 Scheme)
EE707 Advanced Electrical Engineering Lab Manual (2006 Scheme)
EE707 Advanced Electrical Engineering Lab Manual (2006 Scheme)
ACKNOWLEDGEMENT
Any suggestions for the improvement of this manual will be acknowledged and appreciated. ANITH KRISHNAN
INTRODUCTION
EE 707 - Advanced Electrical Engineering Lab is a part of the course study of the students of Electrical Engineering registered under CUSAT. The students are advised to refer standard textbooks along with this laboratory manual to have a thorough understanding of the concepts and the principles involved.
INSTRUCTIONS
Discipline has to be maintained throughout the lab session. All students should wear shoes. Male students should tuck in their shirts. Students should not lean on the work bench or on the computer table. Do not switch on the supply before the circuit is veried by the concerned lab faculty. Shutdown the computer before leaving the lab. Use of mobile phone inside the laboratory is strictly prohibited. Entry will be allowed only to students who have their rough record and fair record (completed) in custody. Use of USB drives, CDs, DVDs or any other portable data storage device without the permission of the lab in-charge is forbidden. All the students are to strictly abide by the instructions given here and any additional instruction given during the lab session, failing to which he/she will have to face disciplinary action.
Contents
Familiarization of MATLAB I. Familiarization of MATLAB II. Familiarization of MATLAB III. Familiarization of SIMULINK. Modelling and Simulation of Mechanical Translational System. Lead Compensator. Lag Compensator. Comparison of Lag Compensated and Lead Compensated System. PID Control System. Synchro. Steady-State Stability Analysis. Bus Admittance Matrix. LVDT. Step Response of Second Order System. Diode Rectier circuits. 1 3 5 7 10 12 14 16 17 20 21 24 28 29 30
2006 Scheme
Experiment No.: 1
FAMILIARIZATION OF MATLAB I
Aim: To familiarize with some basic commands in MATLAB. Main Window:
Some Basic Commands: To store a row matrix A = 1 2 3 >> A=[1 2 3] 1 2 To store a column matrix, A = 3 >> A=[1;2;3]
2006 Scheme
1 2 3 To store a square matrix, A = 4 5 6 7 8 9 >> A=[1 2 3;4 5 6;7 8 9] To nd the inverse of matrix A >> A=[1 2;3 4] >> inv(A) gives the answer 2 1 1.5 0.5
To nd the determinant of A >> det(A) gives the answer 2 Multiplication of two matrices, A = >> A=[1 2;3 4] >> B=[4 3;2 1] >> A*B gives the answer 8 5 20 13
2 2
1 2 4 3 and B = 3 4 2 1
1 2 Square of a matrix A = 3 4 >> A=[1 2;3 4] >> A^2 gives the answer Result: 7 10 15 22
Note: The students are expected to learn all the commands not given in this manual as and when required. Department of Electrical and Electronics Engineering, College of Engineering, Thalassery 2
2006 Scheme
Experiment No.: 2
FAMILIARIZATION OF MATLAB II
Aim: To familiarize with some basic commands in MATLAB related to electrical engineering. Commands and their usage: Realize a transfer function G(s) = 1 s2 + 2s + 5
>> num=[1] % coefficients of numerator >> den=[1 2 5] % coefficients of denominator >> G=tf(num,den) The transfer function can also be realized directly as shown below >> G=tf([1],[1 2 5]) Multiplication of two transfer functions G1(s) = >> G1=tf([1],[1 2 5]) >> G2=tf([3],[2 0 5]) >> G1*G2 The answer will be a fourth order transfer function (as evident). To obtain the step response of the system G1(s) = >> G1=tf([1],[1 2 5]) >> step(G1)
Step Response 0.25
1 and G2(s) = 23 s2 + 2s + 5 2s + 5
1 s2 + 2s + 5
0.2
Amplitude
0.15
0.1
0.05
3 Time (sec)
2006 Scheme
To obtain the bode plot of the system G1(s) = >> G1=tf([1],[1 2 5]) >> bode(G1)
Bode Diagram 10 20 Magnitude (dB) 30 40 50 60 70 80 0 45 Phase (deg) 90 135 180 10
1
1 s2 + 2s + 5
10
10 Frequency (rad/sec)
10
To obtain the root locus of the system G1(s) = >> G1=tf([1],[1 3 5 4]) >> rlocus(G1)
Root Locus 4
1 s3 + 3s2 + 5s + 4
Imaginary Axis
4 5
2 Real Axis
Result:
2006 Scheme
Experiment No.: 3
2. In the new window, the commands can be entered in the sequence in which they are meant to be executed. 3. After all the necessary commands are entered, the le is saved using .m extension. 4. The le (all the commands in sequence) can be executed by clicking on the run button on the toolbar or by pressing F5. 5. The commands will be executed, if there was no error in the code. The command prompt will display all the errors (if any).
2006 Scheme
x1 1 + u x2 0
x1 + [0]u x2
Amplitude
10
12
Time (sec)
2006 Scheme
Experiment No.: 4
FAMILIARIZATION OF SIMULINK
Aim: To familiarize with SIMULINK. Introduction: SIMULINK is a Graphical Users Interface (GUI) software which works directly with the block diagram of a control system (rather than dierential equations, or transfer functions) to produce a simulation of the systems response to arbitrary inputs and initial conditions. The basic entity in SIMULINK is a block, which can be selected from a library of commonly used blocks. Alternatively, a user can device special blocks out of the common blocks, Mles, MEX les, C, or Java codes through the S-function facility. Procedure: 1. To open the SIMULINK library browser, double click on the SIMULINK icon on the MATLAB toolbar, or issue the following command at the MATLAB prompt >> simulink
2. Click on the create a new model icon on the SIMULINK toolbar. A window for the new model will open.
Department of Electrical and Electronics Engineering, College of Engineering, Thalassery 7
2006 Scheme
3. Open the subsystem library in the general SIMULINK library browser by doubleclicking on the appropriate icon. The subsystems are: Continuous, Discontinuous, Sinks, Sources etc. 4. Select the required blocks from the subsystems libraries and drag them individually to the open new model window. 5. Once the required blocks are dragged and placed in the new model window, the inports and out-ports of the adjacent blocks can be joined to create a block diagram as desired. Double clicking on each block will open a dialog blox, in which the blocks parameters can be set. 6. Once the block diagram is ready, it is saved into a location on the hard disk drive. 7. In order to simulate the block diagram, click on the play button on the toolbar. If the model created was correct, the simulation will start and the results can be viewed using any of the sink blocks in the model. However, if there was an error, SIMULINK prompts with a diagnostics dialog box which describes what went wrong in the simulation and also what has to be modied in the model for a successful simulation. 8. The simulation can be further rened by adjusting the simulation parameters. SIMULINK provides several simulation parameters that can be adjusted to achieve a desired accuracy in a simulation. A user can select from a number of time-integration schemes, such as Runge-Kutta, Euler, etc and as well as rene the tolerances and time step sizes used for performing the simulation.
2006 Scheme
Result:
Unit Step Response 1.2 1 0.8 Amplitude 0.6 0.4 0.2 0
5 Time (s)
10
15
2006 Scheme
Experiment No.: 5
With the system initially at rest, a force of 25 Newtons is applied at time t = 0. Assume that the mass M = 1 kg, frictional coecient B = 5 N/m/s, and the spring constant K = 25 N/m. Applying Newtons law of motion, the force equation of the system is M Let x1 = x dx x2 = dt then x 1 = x2 1 x2 = [f (t) Bx2 Kx1 ] M The system can be analyzed by simulating the above system to a step input. d2 x dx +B + Kx = f (t) dt2 dt
10
2006 Scheme
Result:
Exercise: Determine the behaviour of the following system using SIMULINK. 2 d3 y d2 y dy + 4 2 + 8 + 10y = 10u(t) 3 dt dt dt
11
2006 Scheme
Experiment No.: 6
LEAD COMPENSATOR
Aim: To design a lead compensator for a system whose open-loop transfer function is given by 5 G(s) = s(s + 2) so that the static velocity error constant kv is 20s1 , the phase margin is atleast 55 and the gain margin is atleast 12dB. Theory: Students are expected to complete this section by themselves. Procedure: Students are expected to complete this section by themselves. Result: G(s)Gc (s) = 20(0.26s + 1) s(0.5s + 1)(0.04s + 1)
Ramp Response 5 4.5 4 3.5 Amplitude 3 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 Time (s) 3 3.5 4 4.5 5 Input Uncompensated System Compensated System
12
2006 Scheme
4.25
4.2 Amplitude
4.05
4 3.95
4.05
4.1
4.15
4.3
4.35
4.4
4.45
Bode Diagram of Compensated System Gm = Inf dB (at Inf rad/sec) , Pm = 58.3 deg (at 10.1 rad/sec) 60 40 Magnitude (dB) Phase (deg) 20 0 20 40 60 80 90
135
180 1 10
10
10 Frequency (rad/sec)
10
10
13
2006 Scheme
Experiment No.: 7
LAG COMPENSATOR
Aim: To design a lag compensator for a system whose open-loop transfer function is given by 5 G(s) = s(s + 2) so that the static velocity error constant kv is 20s1 , the phase margin is atleast 55 and the gain margin is atleast 12dB. Theory: Students are expected to complete this section by themselves. Procedure: Students are expected to complete this section by themselves. Result: G(s)Gc (s) = 20(8.7s + 1) (166.7s + 1)s(0.5s + 1)
Ramp Response 5 4.5 4 3.5 Amplitude 3 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 Time (s) 3 3.5 4 4.5 5 Input Uncompensated System Compensated System
14
2006 Scheme
5.25
5.2 Amplitude
5.05
4.95
5.05
5.1
5.25
5.3
5.35
5.4
Bode Diagram of Compensated System Gm = Inf dB (at Inf rad/sec) , Pm = 58.1 deg (at 0.95 rad/sec) 150 100 50 0 50 100 90 Phase (deg)
Magnitude (dB)
135
180 4 10
10
10
10 Frequency (rad/sec)
10
10
10
15
2006 Scheme
Experiment No.: 8
16
2006 Scheme
Experiment No.: 9
2006 Scheme
Proportional Integral (PI) Control System: 1. 2. 3. 4. 5. Connect test point 1 and 2 and the test point 4 to ground using jumper links. Set all pots P1 to P5 to minimum position. Switch on the unit and see that the supply indicator glows. With the help of DMM, observe the set value (P1) and simulated value (P2). Both these values are 0V. Observe the error signal at the output of the adder, where the set value and the simulated value are subtracted. Also check the nal output. All these values will be at 0V. Now adjust the set value with pot P1 to 1V and simulated process value at 0V with pot P2 and record it in the table. Observe the error signal and the nal output (the nal output rises immediately to about +9V i.e. the saturation level). Press the rst switch in the discharge block and observe the nal output on DMM (the nal output is same as the error signal when the switch is in pressed position and the output goes to positive saturation as soon as the switch is released). Now keep pot P3 in midway position and again press the discharge switch momentarily (when the discharge switch is released, the nal output starts rising towards +ve saturation taking few seconds to reach the same). Repeat the above procedure with a -ve error signal.
6. 7. 8.
9.
10.
Proportional Derivative (PD) Control System: 1. 2. 3. 4. 5. Connect test point 3 and 4 and test point 2 to ground using jumper links. Set all pots P1 to P5 to minimum position. Switch on the unit and see that the supply indicator glows. With the help of DMM, observe the set value (P1) and simulated value (P2). Both these values are 0V. Observe the error signal at the output of the adder, where the set value and the simulated value are subtracted. Also check the nal output. All these values will be at 0V. Now adjust the set value with pot P1 to 1V and simulated process value at 0V with pot P2 and record it in the table. Observe the error signal and the nal output (the nal output is same as the error signal). Press the second switch in the discharge block and observe the nal output on DMM (the nal output goes to +ve saturation level when the switch is pressed and it comes back to the error signal level as soon as the switch is released). Now keep pot P4 in midway position and again press the discharge switch momentarily (the nal output is at +ve saturation when the discharge switch is pressed and discharges to the error signal level when the switch is released taking a longer time as compared to the earlier case).
18
6. 7. 8.
9.
2006 Scheme
10. Repeat the above step with a -ve error signal. Proportional Integral Derivative (PID) Control System: 1. Connect test point 1 to 2 and test point 3 to 4 using jumper links to select the PID mode. 2. Set all pots (P1 to P5) to minimum position. 3. Switch on the supply (the supply indicator glows). 4. Connect one DMM to observe the error signal and the other DMM at the nal output of the proportional block. 5. Adjust the set value with pot P1 to 1V and the simulated process value with pot P2 to 0V. 6. Observe the error signal and the nal output (the nal output will rise immediately to +9V). 7. Press both the discharge switches momentarily (simultaneously) and observe the nal output (the output remains at +ve saturation when switch is pressed, and when switch is released, it tries to discharge to the error signal level due to derivative action and simultaneously due to integral action, since error is +ve, it again rises to saturation level). 8. Now keep pot P3 and P4 in midway position and observe the nal output when both the discharge switches are pressed momentarily. 9. Now adjust pots P1 and P2 such that the error signal is -1V and repeat the above procedure. 10. Observe the eect of changing the error signal from 1V to 3V and then 3V to 1V and observe the nal output. Analyse your results. 11. Similarly, observe the eect of changing the error signal from -1V to -3V and the -3V to -1V and analyse your results. Result:
19
2006 Scheme
Experiment No.: 10
20
2006 Scheme
Experiment No.: 11
E'
X t = 0.2
X12 = 0.3
V = 1.0
' X d = 0 .3
X12 = 0.3
A 60Hz synchronous generator having inertia constant H = 9.94M J/M V A and a transient reactance Xd = 0.3 per unit is connected to an innite bus through a purely reactive circuit as shown in the gure. Reactances are marked on the diagram on a common system base. The generator is delivering real power of 0.6 per unit, 0.8 power factor lagging to an innite bus at a voltage of V = 1 per unit. Assume the per unit damping power coecient is D = 0.138. The generator is operating in the steady state at 0 = 16.79 . The input power is increased by a small amount P = 0.2 per unit. The new steady-state behaviour can be studied by analyzing the step response of the rotor angle and the generator frequency. Modelling: It is given that the input power is increased by a small amount P . The linearized swing equation is thus H d2 d +D + Ps = P 2 f0 dt dt or f0 d2 f0 d f0 + D + Ps = P dt2 H dt H H or in terms of the standard second-order dierential equation, d2 d 2 + 2n + n = u 2 dt dt
21
2006 Scheme
where u = f0 P H f0 n = Ps H D f0 = 2 HPs
The synchronizing coecient Ps is given by Ps = Pmax cos 0 where Pmax (steady-state stability limit) is given by Pmax = |E | |V | X 0.3 = 0.65 2
E = V + jXI where current I is I= The per unit apparant power S= 0.6 cos1 0.8 = 0.75 36.87 0.8 S = 0.75 36.87 V
Transforming to the state variable form by taking x1 = and x2 = = , the state-space representation is given by x1 0 1 = 2 x2 n 2n and y(t) = Matlab Code: A=[0 1;-37.705 -2.617]; Du=3.79; B=[0;1]*Du; C=[1 0;0 1];
Department of Electrical and Electronics Engineering, College of Engineering, Thalassery 22
x1 0 + u x2 1 x1 x2
1 0 0 1
2006 Scheme
D=[0;0]; t=0:0.01:5; [y,x]=step(A,B,C,D,1,t); Dd=x(:,1); Dw=x(:,2); d=d0+Dd)*180/pi; f=f0+Dw/(2*pi); subplot(2,1,1); plot(t,d); grid on; subplot(2,1,2); plot(t,f); grid on; Simulink Block Diagram:
Result:
30 (deg.) 25 20 15
0.5
1.5
2.5
3.5
4.5
f (Hz)
0.5
1.5
3.5
4.5
23
2006 Scheme
Experiment No.: 12
The emfs shown in the gure are E1 = 1.1 0 and E2 = 1.0 0 . Theory and Modelling:
The circuit has been redrawn in terms of admittances and transformation to current sources. With source transformation, the equivalent current sources are 1.1 = j1.1 pu I1 = j1.0 1.0 I2 = = j1.25 pu j0.8
Department of Electrical and Electronics Engineering, College of Engineering, Thalassery 24
2006 Scheme
Node 0 (which is normally ground) is taken as reference. Applying KCL to the independent nodes 1 through 4 reslts in I1 = y10 V1 + y12 (V1 V2 ) + y13 (V1 V3 ) I2 = y20 V2 + y12 (V2 V1 ) + y23 (V2 V3 ) 0 = y23 (V3 V2 ) + y13 (V3 V1 ) + y34 (V3 V4 ) 0 = y34 (V4 V3 ) Rearranging these equations yields I1 = (y10 + y12 + y13 )V1 y12 V2 y13 V3 I2 = y12 V1 + (y20 + y12 + y23 )V2 y23 V3 0 = y13 V1 y23 V2 + (y13 + y23 + y34 )V3 y34 V4 0 = y34 V3 + y34 V4 Let Y11 Y22 Y33 Y44 Y12 Y13 Y23 Y34 = y10 + y12 + y13 = y20 + y12 + y23 = y13 + y23 + y34 = y34 = Y21 = y12 = Y31 = y13 = Y32 = y23 = Y43 = y34
The node equation reduces to I1 I2 I3 I4 = Y11 V1 + Y12 V2 + Y13 V3 + Y14 V4 = Y21 V1 + Y22 V2 + Y23 V3 + Y24 V4 = Y31 V1 + Y32 V2 + Y33 V3 + Y34 V4 = Y41 V1 + Y42 V2 + Y43 V3 + Y44 V4
In the above network, since there is no connection between bus 1 and 4, Y14 = Y41 = 0; similarly Y24 = Y42 = 0. Extending the above relation to an n bus system, the node-voltage equation in matrix form is V1 Y11 Y12 Y1n I1 I2 Y21 Y22 Y2n V2 .= . . . . . . . . . . . . . . Vn Yn1 Yn2 Ynn In
Department of Electrical and Electronics Engineering, College of Engineering, Thalassery 25
2006 Scheme
or Ibus = Ybus Vbus where Ibus is the vector of the injected bus currents (i.e. external current sources). The current is positive when owing towards the bus, and it is negative if owing away from the bus. Vbus is the vector of bus voltages measured from the reference node (i.e. node voltages). Ybus is known as the bus admittance matrix. The diagonal element of each node is the sum of admittances connected to it. It is known as the self-admittance or driving point admittance, i.e.,
n
Yii =
j=0
yij
j=i
The o-diagonal element is equal to the negative of the admittance between the nodes. It is known as the mutual admittance or transfer admittance, i.e., Yij = Yji = yij The inverse of bus admittance matrix is known as the bus impedance matrix Zbus . MATLAB function ybus: A function called Y=ybus(zdata) is written for the formation of the bus admittance matrix. zdata is the line data input and contains four columns. The rst two colmns are the line bus numbers and the remaining columns contain the line resistance and reactance per unit. The function returns the bus admittance matrix. In the program, the line impedances are rst converted to admittances. Y is the initialized to zero. In the rst loop, the line data is searched to nd the elements connected to a bus, and the diagonal elements are thus formed. The following is the program for building the bus admittance matrix: function[Y]=ybus(zdata) nl=zdata(:,1); nr=zdata(:,2); R=zdata(:,3); X=zdata(:,4); nbr=length(zdata(:,1)); nbus=max(max(nl),max(nr)); Z=R+j*X; y=ones(nbr,1)./Z; Y=zeros(nbus,nbus); for k=1:nbr; if nl(k)>0 & nr(k)>0 Y(nl(k),nr(k))=Y(nl(k),nr(k))-y(k); Y(nr(k),nl(k))=Y(nl(k),nr(k));
Department of Electrical and Electronics Engineering, College of Engineering, Thalassery 26
2006 Scheme
end end for n=1:nbus for k=1:nbr if nl(k)==n | nr(k)==n Y(n,n)=Y(n,n)+y(k); else, end end end Matlab Code: % From To R X z = [0 1 0 1.0 0 2 0 0.8 1 2 0 0.4 1 3 0 0.2 2 3 0 0.2 3 4 0 0.08]; Y=ybus(z) Ibus=[-j*1.1; -j*1.25; 0; 0]; Zbus=inv(Y) Vbus=Zbus*Ibus Result:
27
2006 Scheme
Experiment No.: 13
Result:
28
2006 Scheme
Experiment No.: 14
29
2006 Scheme
Experiment No.: 15
Integrated circuits, unlike board-level designs composed of discrete parts, are impossible to breadboard before manufacture. Further, the high costs of photolithographic masks and other manufacturing prerequisites make it essential to design the circuit to be as close to perfect as possible before the integrated circuit is rst built. Simulating the circuit with SPICE is the industry-standard way to verify circuit operation at the transistor level before committing to manufacturing an integrated circuit. Board-level circuit designs can often be breadboarded for testing. Even with a breadboard, some circuit properties may not be accurate compared to the nal printed wiring board, such as parasitic resistances and capacitances. These parasitic components can often be estimated more accurately using SPICE simulation. Also, designers may want more information about the circuit than is available from a single mock-up. For instance, circuit performance is aected by component manufacturing tolerances. In these cases it is common to use SPICE to perform Monte Carlo simulations of the eect of component variations on performance, a task which is impractical using calculations by hand for a circuit of any appreciable complexity. Circuit simulation programs, of which SPICE and derivatives are the most prominent, take a text netlist describing the circuit elements (transistors, resistors, capacitors, etc.) and their connections, and translate this description into equations to be solved. The general equations produced are nonlinear dierential algebraic equations which are solved using implicit integration methods, Newtons method and sparse matrix techniques. Procedure: Students are expected to complete this section by themselves.
Department of Electrical and Electronics Engineering, College of Engineering, Thalassery 30
2006 Scheme
400 Source (primary) Voltage Voltage (V) 200 0 200 400 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
20 40 0 0.005 0.01 0.015 0.02 Time (s) 0.025 0.03 0.035 0.04
31
2006 Scheme
40 Voltage (V) 20 0
Current (A)
0.6 0.4 0.2 0 0.2 0 0.005 0.01 0.015 0.02 Time (s) 0.025 0.03 0.035
IC1
0.04
Result:
32