Baugh Wooley

VLSI Design
Adders and Multipliers
Baugh-Wooley Multiplier Design

To illustrate the mathematical transformation which is required, consider 4-bit signed operands X and Y and an 8-bit product P: X (x3, x2, x1, x0) , Y (y3, y2, y1, y0) , P (p7, p6, p5, p4 ,p3, p2, p1, p0) Because these are in twos complement form, we can compute their numerical values as:
X = x3 2 + xi 2
3 i =0 2 i
Y = y3 2 + y j 2
3 j= 0
P = p7 2 + pi 2i
7 i=0
Also, since P = XY, we can write:

P = ( x 3 2 + xi 2 )( y3 2 + y j 2 j )
3 i 3 i =0 2 j= 0 2 2 2
= x 3y 3 2 +
6
i = 0 j= 0
xi y j 2
i+ j
xi y3 2
i =0
i +3
x 3y j 2 j+ 3
j= 0
Note that the first two terms are positive summands while the second two terms are negative summands. However, instead of subtracting, we can add the twos complements of those two terms. 2011 by Gerald E. Sobelman 34
VLSI Design
Baugh-Wooley Multiplier - Cont.

Consider the summation in the 3rd term. We can add 2 zero terms that dont change it: 2 2 i+3 3 4 3 x i y 3 2 = 2 [ 0 2 + 0 2 + x i y 3 2 i ]
i=0 i=0
Instead of subtracting this, we can add its twos complement, which can be computed as the ones complement plus 1:
2 [ 1 2 + 1 2 +
3 4 3
i=0
x i y 3 2 i + 1]
There are two possible cases: If y3 = 0, this simplifies to:

2 [ 2 +
3 3 i=0
2 i + 1] = 2 3[ 2 3 + ( 2 3 1) + 1] = 0
If y3 = 1, this simplifies to:

2 [ 2 +
3 3
i=0
x i 2 i + 1]
35
Ref: K. Hwang, Computer Arithmetic: Principles, Architecture and Design, John Wiley, 1979.
2011 by Gerald E. Sobelman
VLSI Design
Baugh-Wooley Multiplier Design Cont.

These two sub-cases can be subsumed into the following single expression:
2 [ 2 + y 3 + y 3 2 + x i y 3 2 i ]
3 3 3 i=0
We can check this as follows: For y3 = 0, this reduces to: 2 3 [ 2 3 + 2 3 ] = 0 For y3 = 1, this reduces to: 2 [ 2 + 1 + x i 2 i ]
3 3 i=0 2

By symmetry (i.e., by reversing the roles of the x and y terms), we can immediately write down the corresponding expression for the twos complement of the 4th term as:
2 3[ 2 3 + x 3 + x 3 2 3 +
j= 0
x3 y j 2 j ]
36
VLSI Design

Finally, replacing the negative summands by the addition of these twos complement forms in our original expression for P gives:
P = x 3y 3 2 +
6 6 i = 0 j= 0 3
xi y j 2i+ j
6 i=0 2
2 + y3 2 + y3 2 + 26 + x3 23 + x3 26 +
xi y3 2i+3
j= 0
x 3 y j 2 j+ 3
Note that we can further simplify -26 - 26 = -27, which, in turn, corresponds to a +1 in the 27 position because it is the MSB of an 8-bit twos complement vector. As a result, the above set of terms corresponds to a set of positive terms to be added using a set of half-adders and full-adders. The above mathematical transformations can be extended to an arbitrary operand sizes, such as 16-bit by 16-bit multiplication or 32-bit by 32-bit multiplication, etc.
37
VLSI Design
38
VLSI Design
Verilog Code for the Baugh-Wooly Multiplier: Part 1 of 3

// half adder component used in the multiplier module half_adder(a, b, s, cout); input a, b; output s, cout; assign s = a^b; assign cout = a&b; endmodule // full adder component used in the multiplier module full_adder(a, b, cin, s, cout); input a, b, cin; output s, cout; assign s = a^b^cin; assign cout = (a&b) | (b&cin) | (a&cin); endmodule
39
VLSI Design

// 4-bit by 4-bit Baugh-Wooley signed multiplier module mult4bw(x, y, p); input [3:0] x, y; output [7:0] p; // constant logic-one value supply1 one; // internal nodes within the multiplier circuit wire t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, t19, t20, t21, t22, t23;
40
VLSI Design

// structural description of the multiplier circuit assign p[0] = x[0]&y[0]; half_adder ha1(x[1]&y[0], x[0]&y[1], p[1], t1); half_adder ha2(x[2]&y[0], x[1]&y[1], t2, t3); full_adder fa1(t2, t1, x[0]&y[2], p[2], t4); half_adder ha3(x[3]&~y[0], x[2]&y[1], t5, t6); full_adder fa2(t5, t3, x[1]&y[2], t7, t8); full_adder fa3(t7, t4, ~x[0]&y[3], t9, t10); full_adder fa4(t9, x[3], y[3], p[3], t11); full_adder fa5(x[3]&~y[1], t6, x[2]&y[2], t12, t13); full_adder fa6(t12, t8, ~x[1]&y[3], t14, t15); full_adder fa7(t14, t10, t11, p[4], t16); full_adder fa8(x[3]&~y[2], t13, ~x[2]&y[3], t17, t18); full_adder fa9(t17, t15, t16, p[5], t19); full_adder fa10(~x[3], ~y[3], x[3]&y[3], t20, t21); full_adder fa11(t20, t18, t19, p[6], t22); full_adder fa12(one, t21, t22, p[7], t23); endmodule
41
VLSI Design
An Exhaustive Testbench for the B-W Multiplier: Part 1 of 3

module tb9; // testbench for the 4-bit by 4-bit Baugh-Wooley signed multiplier // exhaustive checking of all 256 possible cases reg [3:0] integer wire [7:0] integer integer integer integer integer x, y; xval, yval; p; pval; check; i, j; num_correct; num_wrong; // // // // // // // // 4-bit inputs (to be chosen randomly) numerical values of inputs x and y 8-bit output of the multiplier circuit numerical value of the product value used to check correctness loop variables counter to keep track of the number correct counter to keep track of the number wrong
// instantiate the 4-bit by 4-bit Baugh-Wooley signed multiplier mult4bw mult_instance(x, y, p); // exhaustive simulation of all 256 possible cases initial begin // initialize the counter variables num_correct = 0; num_wrong = 0;
42
VLSI Design

// loop through all possible cases and record the results for (i = 0; i < 16; i = i + 1) begin x = i; xval = -x[3]*8 + x[2:0]; for (j = 0; j < 16; j = j + 1) begin y = j; yval = -y[3]*8 + y[2:0]; check = xval * yval; // compute and check the product #10 pval = -p[7]*128 + p[6:0]; if (pval == check) num_correct = num_correct + 1; else num_wrong = num_wrong + 1; // following line is commented out, but is useful for debugging // $display($time, " %d * %d = %d (%d)", xval, yval, pval, check); end end
43
VLSI Design

// print the final counter values $display("num_correct = %d, num_wrong = %d", num_correct, num_wrong); end endmodule
The output produced by this testbench is:
num_correct =
256, num_wrong =
44

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How does the Baugh-Wooley algorithm mathematically transform the multiplication operation into a series of additions?

How does the Baugh-Wooley algorithm mathematically transform the multiplication operation into a series of additions?

What are the main components (half adder, full adder) used to implement the Baugh-Wooley multiplier in Verilog?

What are the main components (half adder, full adder) used to implement the Baugh-Wooley multiplier in Verilog?

VLSI Design

Adders and Multipliers

Baugh-Wooley Multiplier Design

Also, since P = XY, we can write:

Adders and Multipliers

Baugh-Wooley Multiplier - Cont.

There are two possible cases: If y3 = 0, this simplifies to:

If y3 = 1, this simplifies to:

2011 by Gerald E. Sobelman

Adders and Multipliers

Baugh-Wooley Multiplier Design Cont.

2011 by Gerald E. Sobelman

Adders and Multipliers

Baugh-Wooley Multiplier Design Cont.

2011 by Gerald E. Sobelman

Adders and Multipliers

Baugh-Wooley Multiplier Design Cont.

2011 by Gerald E. Sobelman

Adders and Multipliers

Verilog Code for the Baugh-Wooly Multiplier: Part 1 of 3

2011 by Gerald E. Sobelman

Adders and Multipliers

Verilog Code for the Baugh-Wooly Multiplier: Part 2 of 3

2011 by Gerald E. Sobelman

Adders and Multipliers

Verilog Code for the Baugh-Wooly Multiplier: Part 3 of 3

2011 by Gerald E. Sobelman

Adders and Multipliers

An Exhaustive Testbench for the B-W Multiplier: Part 1 of 3

2011 by Gerald E. Sobelman

Adders and Multipliers

An Exhaustive Testbench for the B-W Multiplier: Part 2 of 3

2011 by Gerald E. Sobelman

Adders and Multipliers

An Exhaustive Testbench for the B-W Multiplier: Part 3 of 3

The output produced by this testbench is:

2011 by Gerald E. Sobelman

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