FEBRUARY 2001

DSC-2946/9
1
2000 Integrated Device Technology, Inc.
Features
N NN NN
High-speed address/chip select time
Military: 25/35/45/55/70/85/100ns (max.)
Industrial: 25/35ns (max.)
Commercial: 20/25/35ns (max.) low power only
N NN NN
Low-power operation
N NN NN
Battery Backup operation 2V data retention
N NN NN
Produced with advanced high-performance CMOS
technology
N NN NN
Input and output directly TTL-compatible
N NN NN
Available in standard 28-pin (300 or 600 mil) ceramic DIP,
28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ and
32-pin LCC
N NN NN
Military product compliant to MIL-STD-883, Class B
Functional Block Diagram
Description
The IDT 71256 is a 262,144-bit high-speed static RAM organized as
32K x 8. It is fabricated using IDT's high-performance, high-reliability
CMOS technology.
Address access times as fast as 20ns are available with power
consumption of only 350mW (typ.). The circuit also offers a reduced power
standby mode. When CS goes HIGH, the circuit will automatically go to and
remain in, a low-power standby mode as long as CS remains HIGH. In
the full standby mode, the low-power device consumes less than 15W,
typically. This capability provides significant system level power and
cooling savings. The low-power (L) version also offers a battery backup
data retention capability where the circuit typically consumes only 5W
when operating off a 2V battery.
The IDT71256 is packaged in a 28-pin (300 or 600 mil) ceramic DIP,
a 28-pin 300 mil SOJ, a 28-pin (600 mil) plastic DIP, and a 32-pin LCC
providing high board level packing densities.
The IDT71256 military RAM is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance and
reliability.
CMOS Static RAM
256K (32K x 8-Bit)
IDT71256S
IDT71256L
A0
ADDRESS
DECODER
262,144 BIT
MEMORY ARRAY
I/O CONTROL
2946 drw 01
INPUT
DATA
CIRCUIT
WE
CS
VCC
GND
A14
I/O0
I/O7
CONTROL
CIRCUIT
OE
,
2
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Absolute Maximum Ratings
{1}
Pin Configurations
DP/8OJ
Top View
Truth Table
{1}
32-Pin LCC
Top View
2946 drw 02
5
6
7
8
9
10
11
12
GND
1
2
3
4
24
23
22
21
20
19
18
17
D28-3
P28-1
D28-1
SO28-5
13
14
28
27
26
25
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VCC A14
WE
A13
A8
A10
A11
OE
A12
CS
I/O7
I/O6
I/O5
I/O4
I/O3
A9
16
15
5
6
7
8
9
L32-1
20 19 18 17
10
11
12
13
1
V
16 15
2946 drw 03
14
4
A
3
A
1
,
1
INDEX
2
21
22
23
24
25
26
27
28
29
32 31 30
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CS
I/O7
I/O8
A
7
A
1
2
A
1
4
N
C
V
C
C
W
E
A
1
3
I
/
O
1
I
/
O
2
G
N
D
N
C
I
/
O
3
I
/
O
4
I
/
O
5
,
Pin Descriptions
Name Description
A0 - A14 Address Inputs
I/O0 - I/O7 Data Input/Output
CS Chip Select
WE Write Enable
OE Output Enable
GND Ground
VCC Power
2946 tbl 01
Capacitance {TA = +25C, f = 1.0MHz}
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
NOTE:
1. H = VIH, L = VIL, X = Don't care.
WE CS OE I/O Function
X H X High-Z Standby (ISB)
X VHC X High-Z Standby (ISB1)
H L H High-Z Output Disabled
H L L DOUT Read Data
L L X DIN Write Data
2946 tbl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol Rating Com'l. Ind. Mil. Unit
VTERM Terminal Voltage
with Respect
to GND
-0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 V
TA Operating
Temperature
0 to +70 -40 to +85 -55 to +125
o
C
TBIAS Temperature
Under Bias
-55 to +125 -55 to +125 -65 to +135
o
C
TSTG
Storage
Temperature
-55 to +125 -55 to +125 -65 to +150
o
C
PT
Power
Dissipation
1.0 1.0 1.0 W
IOUT DC Output Current 50 50 50 mA
2946 tbl 03
Symbol Parameter
(1)
Conditions Max. Unit
CIN Input Capacitance VIN = 0V 11 pF
CI/O I/O Capacitance VOUT = 0V 11 pF
2946 tbl 04
6.42
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
3
Recommended Operating
Temperature and 8upply Voltage
Recommended DC Operating
Conditions
NOTE:
1. VIL (min.) = 3.0V for pulse width less than 20ns, once per cycle.
Grade Temperature GND Vcc
Military -55
O
C to +125
O
C 0V 5V 10%
Industrial -40
O
C to +85
O
C 0V 5V 10%
Commercial 0
O
C to +70
O
C 0V 5V 10%
2946 tbl 05
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
VIH Input High Voltage 2.2
____
6.0 V
VIL Input Low Voltage -0.5
(1) ____
0.8 V
2946 tbl 06
DC Electrical Characteristics
{1,2}
{VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V}
71256S/L20 71256S/L25 71256S/L35 71256S/L45
Symbol Parameter
Power Com'l. Mil. Com'l
& Ind
Mil. Com'l.
& Ind
Mil. Com'l. Mil.
Unit
ICC Dynamic Operating Current
CS < VIL, Outputs Open
VCC = Max., fMAX
(2)
S
____ ____ ____
150
____
140
____
135 mA
L 135
____
115 130 105 120
____
115
ISB Standby Power Supply Current
(TTL Level), CS > VIH, VCC = Max.,
Outputs Open, f = fMAX
(2)
S
____ ____ ____
20
____
20
____
20 mA
L 3
____
3 3 3 3
____
3
ISB1 Full Standby Power Supply Current
(CMOS Level), CS > VHC,
VCC = Max. , f = 0
S
____ ____ ____
20
____
20
____
20 mA
L 0.4
____
0.4 1.5 0.4 1.5
____
1.5
2946 tbl 07
71256S/L55 71256S/L70 71256S/L85 71256S/L100
Symbol Parameter Power Mil. Mil. Mil. Mil. Unit
ICC Dynamic Operating Current
CS < VIL, Outputs Open
VCC = Max., fMAX
(2)
S 135 135 135 135 mA
L 115 115 115 115
ISB Standby Power Supply Current
(TTL Level), CS > VIH, VCC = Max.,
Outputs Open, f = fMAX
(2)
S 20 20 20 20 mA
L 3 3 3 3
ISB1 Full Standby Power Supply Current
(CMOS Level), CS > VHC,
VCC = Max. , f = 0
S 20 20 20 20 mA
L 1.5 1.5 1.5 1.5
2946 tbl 08
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, all address inputs are cycling at fMAX; f = 0 means no address pins are cycling.
4
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
AC Test Conditions
*Includes scope and jig capacitances
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
Figure 1. AC Test Load
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Fi gures 1 and 2
2946 tbl 09
2946 drw 04
480
255
30pF*
DATAOUT
5V
,
2946 drw 05
480
255
5pF*
DATAOUT
5V
,
DC Electrical Characteristics {VCC = 5.0V 10%}
Data Retention Characteristics Over All Temperature Ranges
{L Version Only} {VLC = 0.2V, VHC = VCC - 0.2V}
NOTES:
1. TA = +25C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
Symbol Parameter Test Conditions
IDT71256S IDT71256L
Unit Min. Typ. Max. Min. Typ. Max.
|ILI| Input Leakage Current VCC = Max.,
VIN = GND to VCC
MIL.
COM"L & IND.
____
____
____
____
10
5
____
____
____
____
5
2
A
|ILO| Output Leakage Current VCC = Max., CS = VIH,
VOUT = GND to VCC
MIL.
COM"L & IND.
____
____
____
____
10
5
____
____
____
____
5
2
A
VOL Output Low Voltage IOL = 8mA, VCC = Min.
____ ____
0.4
____ ____
0.4 V
IOL = 10mA, VCC = Min.
____ ____
0.5
____ ____
0.5
VOH Output High Voltage IOH = -4mA, VCC = Min. 2.4
____ ____
2.4
____ ____
V
2946 tbl 10
Typ.
(1)
VCC @
Max.
VCC @
Symbol Parameter Test Condition Min. 2.0V 3.0V 2.0V 3.0V Unit
VDR VCC for Data Retention
____
2.0
____ ____ ____ ____
V
ICCDR
Data Retention Current MIL.
COM'L. & IND.
____
____
____
____
____
____
500
120
800
200
A
tCDR
Chip Deselect to Data
Retention Time
CS > VHC
0
____ ____ ____ ____
ns
tR
(3)
Operation Recovery Time tRC
(2) ____ ____ ____ ____
ns
2946 tbl 11
6.42
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
5
AC Electrical Characteristics {VCC = 5.0V 10%, All Temperature Ranges}
Low VCC Data Retention Waveform
2946 drw 06
DATA
RETENTION
MODE
4.5V
4.5V
VDR 2V
VIH VIH
tR tCDR
VCC
CS
VDR
NOTES:
1. 0 to +70C temperature range only.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 55C to +125C temperature range only.
Symbol Parameter
71256L20
(1)
71256S25
71256L25
71256S35
71256L35
71256S45
(3)
71256L45
(3)
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 20
____
25
____
35
____
45
____
ns
tAA Address Access Time
____
20
____
25
____
35
____
45 ns
tACS Chip Select Access Time
____
20
____
25
____
35
____
45 ns
tCLZ
(2)
Chip Select to Output in Low-Z 5
____
5
____
5
____
5
____
ns
tCHZ
(2)
Chip Deselect to Output in High-Z
____
10
____
11
____
15
____
20 ns
tOE Output Enable to Output Valid
____
10
____
11
____
15
____
20 ns
tOLZ
(2)
Output Enable to Output in Low-Z 2
____
2
____
2
____
0
____
ns
tOHZ
(2)
Output Disable to Output in High-Z 2 8 2 10 2 15
____
20 ns
tOH Output Hold from Address Change 5
____
5
____
5
____
5
____
ns
Write Cycle
tWC Write Cycle Time 20
____
25
____
35
____
45
____
ns
tCW Chip Select to End-of-Write 15
____
20
____
30
____
40
____
ns
tAW Address Valid to End-of-Write 15
____
20
____
30
____
40
____
ns
tAS Address Set-up Time 0
____
0
____
0
____
0
____
ns
tWP Write Pulse Width 15
____
20
____
30
____
35
____
ns
tWR Write Recovery Time 0
____
0
____
0
____
0
____
ns
tDW Data to Write Time Overlap 11
____
13
____
15
____
20
____
ns
tWHZ
(2)
Write Enable to Output in High-Z
____
10
____
11
____
15
____
20 ns
tDH Data Hold from Write Time 0
____
0
____
0
____
0
____
ns
tOW
(2)
Output Active from End-of-Write 5
____
5
____
5
____
5
____
ns
2946 tbl 12
6
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics {VCC = 5.0V 10%, Military Temperature Ranges}
NOTES:
1. -55 to +125C temperature range only.
2. This parameter is guaranteed by device characterization, but is not production tested.
Symbol Parameter
71256S55
(1)
71256L55
(1)
71256S70
(1)
71256L70
(1)
71256S85
(1)
71256L85
(1)
71256S100
(1)
71256L100
(1)
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55
____
70
____
85
____
100
____
ns
tAA Address Access Time
____
55
____
70
____
85
____
100 ns
tACS Chip Select Access Time
____
55
____
70
____
85
____
100 ns
tCLZ
(2)
Chip Select to Output in Low-Z 5
____
5
____
5
____
5
____
ns
tCHZ
(2)
Chip Deselect to Output in High-Z
____
25
____
30
____
35
____
40 ns
tOE Output Enable to Output Valid
____
25
____
30
____
35
____
40 ns
tOLZ
(2)
Output Enable to Output in Low-Z 0
____
0
____
0
____
0
____
ns
tOHZ
(2)
Output Disable to Output in High-Z 0 25 0 30
____
35
____
40 ns
tOH Output Hold from Address Change 5
____
5
____
5
____
5
____
ns
Write Cycle
tWC Write Cycle Time 55
____
70
____
85
____
100
____
ns
tCW Chip Select to End-of-Write 50
____
60
____
70
____
80
____
ns
tAW Address Valid to End-of-Write 50
____
60
____
70
____
80
____
ns
tAS Address Set-up Time 0
____
0
____
0
____
0
____
ns
tWP Write Pulse Width 40
____
45
____
50
____
55
____
ns
tWR Write Recovery Time 0
____
0
____
0
____
0
____
ns
tDW Data to Write Time Overlap 25
____
30
____
35
____
40
____
ns
tWHZ
(2)
Write Enable to Output in High-Z
____
25
____
30
____
35
____
40 ns
tDH Data Hold from Write Time (WE) 0
____
0
____
0
____
0
____
ns
tOW
(2)
Output Active from End-of-Write 5
____
5
____
5
____
5
____
ns
2946 tbl 13
6.42
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
7
Timing Waveform of Read Cycle No. 2
{1,2,4}
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured 200mV from steady state.
Timing Waveform of Read Cycle No. 1
{1}
ADDRESS
CS
OE
DATAOUT
tRC
tAA
tOH
tOE
tACS
tCLZ
(5)
tOLZ
(5)
2946 drw07
tCHZ
(5)
tOHZ
(5)
2946 drw 08
ADDRESS
DATAOUT
tRC
tAA
tOH
tOH
,
Timing Waveform of Read Cycle No. 2
{1,3,4}
CS
DATAOUT
tACS
tCLZ
(5)
2946 drw 09
tCHZ
(5)
8
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 {WE Controlled Timing}
{1,2,4,6}
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured 200mV from steady state.
6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width can be as short
as the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.
Timing Waveform of Write Cycle No. 2 {CS Controlled Timing}
{1,2,4}
CS
2946 drw 10
tAW
tWR
tDW
DATAIN
ADDRESS
t WC
WE
t WP
tDH
DATAOUT
tWZ
t
t AS
(5)
(3)
OE
(3)
(6)
OW
tOHZ
(5)
t WR
CS
2946 drw11
tAW
tDW
DATAIN
ADDRESS
tWC
WE
tCW
tDH2
AS t t
(6)
6.42
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
9
Ordering nformation - Commercial & ndustrial
Ordering nformation - Military
X
Power Speed
XXX
Package
X
Process/
Temperature
Range
B Military (55C to +125C)
Compliant to MIL-STD-883, Class B
TD
D
L32
300 mil CERDIP (D28-3)
600 mil CERDIP (D28-1)
Leadless Chip Carrier (32-pin) (L32-1)
25
35
45
55
70
85
100
S
L
Standard Power
Low Power
Device
Type
71256 IDT
Speed in nanoseconds
2946 drw 12
XXX
X
Power
XX
Speed
XXX
Package
X
Process/
Temperature
Range
Blank
I
Commercial (0C to +70C)
Industrial (-40C to +85C)
Y
P
300 mil SOJ (SO28-5)
600 mil Plastic DIP (P28-1)
20
25
35
L Low Power Only
Device
Type
71256 IDT
Speed in nanoseconds
2946 drw 13
,
300 mil SOJ Only, Commercial Only
10
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Datasheet Document History
11/4/99 Updated to new format
Pp. 15, 9 Added Industrial Temperature Range offerings
Pg. 1 Removed 30, 120, and 150ns military and 45ns commercial speed grade offerings.
Pg. 2 Removed P28-2 package from DIP/SOJ Top View
Pg. 3 Removed 30ns and 45ns (Commercial only) speed grade offerings from DC Electrical table
Revised notes and footnotes
Pg. 5 Removed 30ns speed grade offering from AC Electrical table
Revised notes and footnotes
Pg. 6 Expressed Military Temperature range on AC Electrical table
Revised notes and footnotes
Pg. 8 Removed Note 1 and renumbered notes and footnotes
Pg. 9 Revised Ordering Information and presented by temperature range offering
Pg. 10 Added Datasheet Document History
08/09/00 Not recommended for new designs
02/01/01 Remove "Not recommended for new designs"
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