Synopsys Users Group (SNUG)’s Post

"Exploring #CXL Memory Disaggregation: Use Cases and System Benefits" by Jungmin Choi, Memory System Architect, SK hynix and Myoungseo (Matthew) Kim, Ph.D. , Director, Systems and Computer Architect, SK hynix https://lnkd.in/epJcNHGr In this session, we dive into powerful use cases for DCD (Dynamic Capacity Device) based memory pooling and sharing specified in CXL 3.1 that can reduce costs from a datacenter operations perspective. Each host connected to the memory pool can manage resources flexibly through dynamic memory allocation. We also address use cases for system benefits, such as optimal memory tiering and data placement that each host can achieve through telemetry including hotness tracking provided by the device. Regarding memory sharing, we analyze the characteristics of HPC/AI workloads and explore performance improvement through control and data path optimization between hosts. Specifically, we focus on distributed computing frameworks such as Spark and Ray, which suffer from heavy network traffic and memory duplication due to data object sharing. Through HW/SW system implementation and concrete performance studies, we provide insight into CXL memory pooling and sharing within a multi-host environment. #chiplet #semiconductor

Asterfusion offers the best #AIswitch based on #Ethernet, featuring high-density ports & extremely #lowlatency! Our "Rail-only" architecture reduces the number of links between GPU servers, ensuring optimal performance and cost-efficiency. By utilizing this architecture, we have decreased costs by 75% compared to the legacy full-mesh architecture. Moreover, we have minimized communication overhead with the implementation of only one layer of rail switches, resulting in #ultralowlatency. As the network expands, Asterfusion is capable of providing crossrail switches equipped with #800G ports, meeting all your requirements. For test data of comparing Asterfusion #ROCEv2-based AI switch with #InfiniBand in #AIGC, #HPC #DistributedStorage scenarios test data , refer to : https://lnkd.in/gTCV2nPH #AIswitch #ROCEswitch #lowlatencyswitch #IBswitch #AIGCnetworksolution

HBM3E: All About Bandwidth. The rapid rise in size and sophistication of AI/ML training models requires increasingly powerful hardware deployed in the data center and at the network edge. This growth in complexity and data stresses the existing infrastructure, driving the need for new and innovative processor architectures and associated memory subsystems... Read more in the Cadence blog article>> https://ow.ly/Q5je50TmxQm

HBM3E: All About Bandwidth. The rapid rise in size and sophistication of AI/ML training models requires increasingly powerful hardware deployed in the data center and at the network edge. This growth in complexity and data stresses the existing infrastructure, driving the need for new and innovative processor architectures and associated memory subsystems... Read more in the Cadence blog article>> https://ow.ly/Q5je50TmxQm

HBM3E: All About Bandwidth. The rapid rise in size and sophistication of AI/ML training models requires increasingly powerful hardware deployed in the data center and at the network edge. This growth in complexity and data stresses the existing infrastructure, driving the need for new and innovative processor architectures and associated memory subsystems... Read more in the Cadence blog article>> https://ow.ly/Q5je50TmxQm

HBM3E: All About Bandwidth. The rapid rise in size and sophistication of AI/ML training models requires increasingly powerful hardware deployed in the data center and at the network edge. This growth in complexity and data stresses the existing infrastructure, driving the need for new and innovative processor architectures and associated memory subsystems... Read more in the Cadence blog article>> https://ow.ly/Q5je50TmxQm

Microchip's Eric Colard explains how #5G architecture changes require synchronization. Depending on the location and #network site, those timing requirements require different PTP profiles and PTP capacity. https://lnkd.in/e8ZYqf84 #5gtechnology #5gnetworks

Synopsys Inc has announced the launch of Ultra Ethernet IP and UALink IP solutions that are designed to meet the demands required to scale AI architectures. https://lnkd.in/eyDkqynk

HBM3E: All About Bandwidth. The rapid rise in size and sophistication of AI/ML training models requires increasingly powerful hardware deployed in the data center and at the network edge. This growth in complexity and data stresses the existing infrastructure, driving the need for new and innovative processor architectures and associated memory subsystems... Read more in the Cadence blog article>> https://ow.ly/Q5je50TmxQm

The EXA64100 is based on programmable switching fabric, an advanced multi-core, industry-leading programmable switch chip architecture. This platform allows all filtering features to be implemented at the hardware level for unmatched throughput and performance. The EXA64100 enables high-performance deep protocol identification and processing and data message pre-processing at the chip forwarding logic level. The multi-layer filtering capabilities of the EXA64100 are a powerful feature of this device, enabling enhanced network visibility and better network performance. https://lnkd.in/dH-Gewvu #Cubro #NetworkPacketBroker #NetworkVisibility #NetworkPerformance