Suvadip Chakraborty’s Post

Memory Consistency Models: The cause of, and solution to, all your multicore performance problems. #computing #edu

part #2 The choice of 8 as the base in octal representation is closely tied to the binary system and the way computers store and process information. Let's explore the relationship between octal and binary: Binary System Foundation: Computers fundamentally use the binary system (base-2) for representation because electronic circuits can easily distinguish between two states (on/off or high/low), making it efficient for computation. Binary to Octal Conversion: Octal is a base-8 numeral system, which means it uses eight digits (0, 1, 2, 3, 4, 5, 6, 7). Each octal digit corresponds to three binary digits (bits). Octal is a convenient representation for grouping binary digits in sets of three. This grouping helps simplify the representation of binary numbers and make them more manageable. Memory Organization: In computer memory, data is often organized in groups of bits. Octal provides a concise representation when dealing with binary-coded information, as each octal digit represents three bits. Ease of Human Interpretation: Octal digits are easier for humans to work with mentally than binary digits. A single octal digit corresponds to a specific set of three bits, making it more readable and manageable when dealing with large binary numbers. History and Tradition: The use of octal in computing dates back to early computer systems where hardware architecture and memory organization influenced the choice of number bases. Octal was used as a convenient way to represent and visualize binary-coded information. While octal has historical significance, it is less commonly used in contemporary computing compared to hexadecimal (base-16). Hexadecimal provides an even more compact representation because each digit corresponds to four bits, aligning well with modern computer architectures. However, both octal and hexadecimal serve as intermediate representations between binary and human-readable formats, facilitating communication and understanding in various computing contexts.

Such a brilliant way of differentiating the two ✅. It's not always apparent how important latency and throughput are in data analytics until you're in the thick of it. Whether you're deploying a machine learning model in production or delivering insights in real-time or on-demand, these factors play a crucial role at different stages of the data analytics lifecycle. Latency affects how quickly your system can respond, which is vital for real-time applications. Throughput, on the other hand, is about how much data you can process in a given time, which is key for handling large datasets efficiently. Knowing what’s important at each stage of the lifecycle helps you deliver your intended output quickly and efficiently.

Vector Computing:-> in vector computing we use directional bit means here there is not i j and k there will directional bit with the bit rather them nbothing we use driedctional bit imagine there is bit 101110 and if it have directionla bit 1110 then we make pair of small bit to make this with directional opertor here vector comuting will have direciotnla operator that will make multiple direction for bit where bit could move with the helpo of vetcor accelarion in it what vector direciton bit will make pairs to full vector bit it will creates mutliple vector bit by that ways there will be imagine 100001010 and have vector bit 11001010 then we part the vector bit 11 00 10 10 then in 110 010 10 in thqat way we move clock wise and anti clock wise then we see that in means 11 to reach 00 what angle achive 00 to 10 clock wise what angle achive 10 to 10 what angle achive the anti clocok wise then in that way we use for operation means we use angle for the oeprations means now the gievn bit will drive with these angle total cos and sine to check this bit directions when we achive this bit direction then we achieve bit direction works total angle we achives tehn we do acostheta and asintheta means 100001010costehat 100001010sintheta then we get the operational then imagine if there is any angualr movement achives in it that makes a directions of vectors then we make evry bit direction maps means 1 whihc direction goes in sin theat 0 ten whihc direction goes then 0 goes whihc direction goes tyhen 0 goes whihc direction then we get the in betwen in finsl destination total modulaos from start point to destinations in it start point to destinations we achive many moduilar then we will convert thme in bit and we perfomr any operarion without use of geats means imagine there is 1 and 0- then you could use angle and you could perform any angle operations 

Diving into Branch Predictors 2/10 One of the foundational works in branch prediction is the research by Tse-Yu Yeh and Yale Patt Their 1991 paper, "Two-level adaptive training branch prediction" and 1992 follow-up, "Alternative Implementations of Two-Level Adaptive Branch Prediction", were pivotal in establishing the use of local and global branch history for making accurate predictions. They also defined key implementation variations like GAp, PAg, PAp, which represent different ways to organize branch history information. This 1991 paper received the ACM MICRO Test of Time Award in 2014! You can access it for free here: 🏆 https://lnkd.in/gzMMbauE https://lnkd.in/gh9Y2Ft5 Short summary of the papers: The proposed technique leveraged two key pieces of information to enhance the prediction accuracy: Branch History: The history of the last 'k' branches (taken or not taken.) This is like the CPU remembering recent decisions. Pattern History: The outcomes of the last 's' instances of a specific pattern of n branches. This is like recognizing recurring situations. Key Mechanisms: History Register (HR): A shift register that keeps track of the outcomes of the 'k' most recently executed branches (can be local or global) Pattern Table (PT): Each entry in this table corresponds to a unique n-bit pattern in the HR. It stores information about how the branch behaved the last 's' times that specific pattern occurred. State Transition Automata: These are FSMs that determine how the information in the PT is updated based on the actual outcome of a branch. They provide the logic for learning from correct and incorrect predictions. Implementation Variations: The different ways to implement this two-level scheme, each with trade-offs in prediction accuracy and hardware cost: Global Adaptive (GAg): A single, global history register and pattern table are shared by all branches in the program. This is the simplest and cheapest to implement, but can be less accurate due to interference between different branches. Per-Address History (PAg): Each branch has its own dedicated history register, but all branches share a single, global pattern table. This offers a balance between accuracy and cost, reducing interference compared to GaG. Per-Address History and Pattern (PAp): Each branch gets its own independent history register and pattern table. This eliminates interference and provides the highest accuracy, but is also the most expensive in terms of hardware resources. These papers provided a crucial foundation for understanding branch prediction. Branch prediction techniques have evolved significantly since then. Stay tuned for Later research and state-of-the-art branch predictors in upcoming posts! 😉 #BranchPrediction #CPUArchitecture #HistoryOfComputing #Microarchitecture #Processors #PerformanceOptimization #ComputerEngineering #TechHistory

The field of DNA computing is fascinating. DNA computing has the potential to create machines that offer significant leaps in speeds and capacities,

This advanced blog post provides a comprehensive exploration of time and space complexity in software development, covering advanced concepts, practical applications in distributed and parallel computing, optimization strategies for specialized hardware, and future trends in algorithmic efficiency.

Latency vs Throughput. What's the difference? If you know it, you probably have a job. Every single engineering team optimizes for these metrics. And here is everything you need to know about them. - 𝐋𝐚𝐭𝐞𝐧𝐜𝐲 🏎️ Refers to the time it takes for a single request to be processed by a system or an ML model. 𝘍𝘢𝘤𝘵𝘰𝘳𝘴 𝘢𝘧𝘧𝘦𝘤𝘵𝘪𝘯𝘨 𝘭𝘢𝘵𝘦𝘯𝘤𝘺: 1. ML model and infrastructure complexity 2. Hardware: The computational power of the servers (CPU, GPU, etc.) 3. Data Transfer: The time it takes to transfer data to and from the model, including network latency. 4. Software practices: Efficient coding practices and optimizations (e.g., pruning, quantization) help reduce latency. - 𝐓𝐡𝐫𝐨𝐮𝐠𝐡𝐩𝐮𝐭 🤹🏻 Refers to how many queries/requests are processed in a specific time. 𝘍𝘢𝘤𝘵𝘰𝘳𝘴 𝘢𝘧𝘧𝘦𝘤𝘵𝘪𝘯𝘨 𝘵𝘩𝘳𝘰𝘶𝘨𝘩𝘱𝘶𝘵: 1. Concurrency: Handling multiple requests simultaneously with parallel processing and multi-threading. 2. Resource Allocation: Proper allocation of computational resources (CPU, GPU, memory) 3. Scalability: The capability to scale horizontally by adding more machines or vertically by upgrading hardware. 4. Batch Processing: Processing in batches improves throughput by reducing the overhead. In general... If you work in research you care more about throughput. In production, however, you focus on latency. Every ms your program takes hurts your sales and conversion rates. If you know how to optimize for both you will always be desirable in the industry. --- If you find this helpful: 👍 React ♻️ Share 💬 Comment So more people can learn. --- What else would you add? #ml #datascience

As we work towards scalable error corrected circuits it is important we make progress on what the criteria for reliable quantum computing which is the error correction version of the DiVincenzo’s criteria. 1. Scalable encoding into well-characterized error-correcting codes 2. The ability to initialize to a simple fixed state and inject magic states 3. Codes suppress errors far below physical errors, and larger codes suppress more errors 4. A universal set of quantum gates 5. A qubit-specific measurement capability With our new paper, we used dynamic circuits to manipulate quantum information during the runtime of the circuit, to demonstrate a key ingredient of the second criteria.

Software Engineering and Constraints with Massively Parallel Processing: If you’ve been around parallel computing a bit, you’ve heard the term “Exascale”. The term exascale refers to a Massively Parallel Processor (MPP) performing an Exaflop, where a FLOP is a floating point operation, and the exa prefix refers to performing 1 quintillion FLOPs per second. Yes, 1 x 10^18 operations in a second. These exascale computers are really an incredibly complex networked layer of high powered Nodes, each containing several processors with several cores each. These are a mix of both CPU and GPU processors. As the landscape for these MPPs has changed, so have the constraints of scaling. Below, I will list an old constraint followed by its partner new constraint if it has one: Old: clock frequency as limiter for performance improvement New: power availability - not enough and harmful for environment Old: FLOPs are biggest cost to system - optimize for compute New: data movement is biggest cost to system - minimize data movt Old: memory scaling - maintain byte per FLOP capacity and bandwidth New: memory scaling - compute is growing 2X faster than capacity or bandwidth Old: Locality - uniform costs within nodes and between nodes New: Locality - must reason about data locality and topology Old: Uniformity - assumed uniform system performance New: Heterogeneity - increasingly non-uniform architecture and performance across nodes and chips Old: Concurrency - modest growth of parallelism by adding new nodes New: Concurrency - exponential growth of parallelism within a chip These are some of the constraints that we need to reason about as engineers or leaders designing systems to leverage these massively parallel systems. I’d be interested to hear additional challenges or constraints in these systems, or disagreements! If you like my content, feel free to follow or connect! #softwareengineering #parallel