Gurudutt B.R

Gurudutt B.R

Austin, Texas, United States
2K followers 500+ connections

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Activity

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Experience

  • Apple Graphic

    Apple

    Austin, Texas, United States

  • -

    Folsom

  • -

    Folsom

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    Bengaluru Area, India

  • -

    Bengaluru Area, India

Education

  • University of Minnesota Graphic

    University of Minnesota-Twin Cities

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    Electrical Engineering Graduate Student working on Low power , High Speed VLSI circuits.

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    Activities and Societies: IEEE SJCE, Young wizards, SpirIT

    - Graduated with a GPA of 8.99 on 10.00 with a Bachelors degree in Instrumentation technology.

Licenses & Certifications

Volunteer Experience

  • Leader

    Tech Sparklers

    - 6 months

    Education

    A group of Fresh Young Engineers at Corporate focusing on Culture, Knowledge Empowerment, Space to act and Branding the organization.
    Some of the activities given to the societies are
    --> Visit to orphanages and teaching school kids every weekend.
    --> Cleaning surrounding areas in the city to spread awareness about cleanliness.
    --> Organizing conferences, cultural events, competitions, outings, for the benefit of people.

  • SAE International Graphic

    Event coordinator

    SAE International

    - Present 10 years 3 months

    Education

    Visit to International Schools in Bangalore and organizing technical events to bring the best out of children.

Courses

  • ASIC design and Verification

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  • Advanced Computer Architecture

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  • Advanced VLSI Design

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  • Analog Electronics

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  • Applied Parallel Programming

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  • Biomedical Instrumentaion

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  • Circuits, Computation and Biology

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  • Digital Image Processing

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  • Digital Logic design

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  • Elecrical and Elecronics measurements

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  • Medical Imaging

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  • Signal Conditioning and Circuits

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  • VHDL and Verilog programming

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  • VLSI Design

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  • VLSI Design 1

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Projects

  • Ultrasound Range Meter

    A distance measuring unit using a pair of ultrasound transceivers was designed. Distance up to 5mts was sensed by the pair of transducers and displayed digitally using LED with a resolution of 0.1 mts.
    The signal conditioning and circuitry was designed and calibrated to provide accurate measurements. The system would detect any obstacle within a range of 5mts and provided accurate results.

  • RTL implementation of Cache controller with victim cache

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    - RTL design of cache controller using Verilog coding
    - Implemented 128bytes direct mapped L1 data cache with 1KB Main memory
    - Designed 8 byte FIFO type victim cache module
    - Optimized area, timing and power for the best performance using Synopsys design vision, design compiler
    - Formal verification performed of the entire module using Formality tool
    - Scan insertion and ATPG performed to increase testability to 98% using Synopsys Tetramax.
    - Layout design using Synopsys IC…

    - RTL design of cache controller using Verilog coding
    - Implemented 128bytes direct mapped L1 data cache with 1KB Main memory
    - Designed 8 byte FIFO type victim cache module
    - Optimized area, timing and power for the best performance using Synopsys design vision, design compiler
    - Formal verification performed of the entire module using Formality tool
    - Scan insertion and ATPG performed to increase testability to 98% using Synopsys Tetramax.
    - Layout design using Synopsys IC compiler with Automatic Place & Route (AP&R)
    - Mealy FSM type approach with 9 states for the system encoded in one hot style.
    - Test bench written for each of the state transition and automated using Perl
    - Test coverage of 95% achieved for the entire design
    - Processor modeled to operate in 1GHz. The Victim cache, main memory, main memory, processor, L1 cache designed in the test bench with only the cache controller as the DUT.

  • Full custom design of 128KB SRAM macro with peripheral circuits

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    - Full chip schematic, layout implementation using HSPICE, Cadence Virtuoso, CosmosScope, and Calibre verification tool with full chip LVS and DRC.
    - Design of standard 6 Transistor SRAM cell with 0.42 um sq. area designed for 1 GHz operating frequency.
    - Analysis of Monte Carlo simulations to determine the Read, Write and Hold SNM with Read SNM : 150mV and Write SNM : 400mV.
    - Design of Row decoder, Column decoder including 9 : 512 row MUX, Sense amplifier, Write driver, Column MUX…

    - Full chip schematic, layout implementation using HSPICE, Cadence Virtuoso, CosmosScope, and Calibre verification tool with full chip LVS and DRC.
    - Design of standard 6 Transistor SRAM cell with 0.42 um sq. area designed for 1 GHz operating frequency.
    - Analysis of Monte Carlo simulations to determine the Read, Write and Hold SNM with Read SNM : 150mV and Write SNM : 400mV.
    - Design of Row decoder, Column decoder including 9 : 512 row MUX, Sense amplifier, Write driver, Column MUX circuits.
    - Implementation of Sleep circuit to reduce leakage power ( by 66%) and Write assist circuit for faster write operations by reducing the cell node voltage to a predetermined value.
    - Design of quadrant style sub-array architecture with all poly routed in horizontal direction to make the layout lithographically friendly.
    - Symmetric and isometric differential amplifiers designed for best performance using the techniques of transistor folding, inter-digitization and common centroid methods.
    - Full chip Layout automated using SKILL and automated tests using PERL
    - All simulations performed at worst case temperature of 80 degree C, Voltage 1.1V

  • Parallel algorithm techniques to reconstruct MRI image using GTX480 GPU

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    15X Speed up achieved in computation time for MRI image reconstruction found after implementing the same algorithm in Cuda C on GTX 480 GPU.

  • Custom layout and design of 16 bit knowles adder circuit

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    - Design and simulation of schematic & layout in Cadence Virtuoso and Synopsys HSPICE.
    - Worst case frequency at 1.1V = 917MHz with power = 0.28 mW.
    - Evaluated using Cosmoscope.
    Standard cells were designed using Euler’s path and optimized using fingering techniques. Grids used for optimized metal routing in top level.
    Layout optimized for the best speed, power and area.

  • Improving cache performance by using dead blocks as virtual victim cache

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    - 2.8% improvement in Instructions per Cycle and 17% decrease in DL2 cache miss rate found after implementing a virtual victim cache using simple scalar when compared to standard Least Recently Used (LRU) algorithm.
    - Benchmarks used : GCC, Gzip, Go and Anagram.
    - Dead block prediction using Counter based dead block predictor.
    - Dead Blocks in cache evicted out instead of victims to save live data in the cache.

    Other creators

  • Transistor Characterization using inverter based 7 stage Ring Oscillator

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    - Full custom design and implementation performed in Cadence Virtuoso and Synopsys HSPICE.
    - Inverter design optimized for equal rise-fall times, frequency and total power. Evaluated using Cosmoscope.
    - Found the Beta ratio of the transistor for the best frequency and maximum fanout of 4.
    - Verification of the design performed using Calibre LVS,DRC and PEX tools.

  • Accident Alert Detecton and Assisting the Victims

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    We did this project with a motivation to reduce the number of road accidents and to assist
    the victims if an accident occurs.Ultrasound range detector was used to alert the driver of nearby obstacles.
    Glass break sensors, Piezo sensors and Smoke detector circuits were designed and implemented to detect
    the condition of an accident. A microcontroller, GPS and GSM modules were used to locate the spot of the accident
    and send a text message to emergency personnel and to the dear ones…

    We did this project with a motivation to reduce the number of road accidents and to assist
    the victims if an accident occurs.Ultrasound range detector was used to alert the driver of nearby obstacles.
    Glass break sensors, Piezo sensors and Smoke detector circuits were designed and implemented to detect
    the condition of an accident. A microcontroller, GPS and GSM modules were used to locate the spot of the accident
    and send a text message to emergency personnel and to the dear ones of the victims. We designed the glass break sensor, smoke detector and the ultrasound range meter and interfaced with ATMEGA32 microcontroller along with the GPS and GSM modules.

    Other creators
    See project

Languages

  • English

    Full professional proficiency

  • Kannada

    Native or bilingual proficiency

  • German

    Limited working proficiency

  • Hindi

    Native or bilingual proficiency

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