Amit Dhir

Amit Dhir

San Jose, California, United States
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Patents

  • AI for Pricing - Automated Data Set Enrinchment, Analysis, and Visualization

    Issued 11,977,565

    Systems, methods, and graphical user interfaces (GUIs) for ingesting and enriching data regarding a plurality of entities are provided. A first data set comprising company data and a second data set comprising customer data are ingested. The first data set is processed to generate a processed data set. The first data set may be processed by applying an entity matching technique, wherein one or more data elements are generated based on whether an entity of the first data set and an entity of the…

    Systems, methods, and graphical user interfaces (GUIs) for ingesting and enriching data regarding a plurality of entities are provided. A first data set comprising company data and a second data set comprising customer data are ingested. The first data set is processed to generate a processed data set. The first data set may be processed by applying an entity matching technique, wherein one or more data elements are generated based on whether an entity of the first data set and an entity of the second data set are commonly associated. The first data set may additionally or alternatively be pro- cessed by applying a statistical matching technique, wherein one or more predicted data elements are generated based on similarity between an entity of the first data set and one or more entities of the second data set.

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  • Integrated circuit and method of employing a processor in an integrated circuit

    Issued US 8,180,919

    According to various embodiments of the present invention, an intelligent framer/mapper integrates the framer, mapper, and the controlling function of the host processor, implemented as either a soft processor or an embedded processor, into a single device, such as a programmable logic device. The use of the soft processor or embedded processors on the device reduces the load on the host processor on the line card. According to some aspects of the invention, the devices takes advantage of an…

    According to various embodiments of the present invention, an intelligent framer/mapper integrates the framer, mapper, and the controlling function of the host processor, implemented as either a soft processor or an embedded processor, into a single device, such as a programmable logic device. The use of the soft processor or embedded processors on the device reduces the load on the host processor on the line card. According to some aspects of the invention, the devices takes advantage of an embedded, dedicated processor and/or soft processor(s) to allow for a distributed processing on a single chip.

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  • Programmable logic device for wireless local area network

    Issued US 7,142,557

    Method and apparatus for a wireless local area network programmable logic device is described. More particularly, a field programmable gate array (FPGA) is coupled to memory having programming instructions for configuring the FPGA with a medium access layer selected from more than one type of medium access layers. A physical layer is hardwired or embedded on the FPGA, or a separate integrated circuit for the physical layer is used. Additionally, the memory comprises programming instructions for…

    Method and apparatus for a wireless local area network programmable logic device is described. More particularly, a field programmable gate array (FPGA) is coupled to memory having programming instructions for configuring the FPGA with a medium access layer selected from more than one type of medium access layers. A physical layer is hardwired or embedded on the FPGA, or a separate integrated circuit for the physical layer is used. Additionally, the memory comprises programming instructions for a baseband controller, and may include programming instructions for a baseband processor, for configuring the FPGA in accordance therewith. In this manner, a single physical layer may be used with an FPGA to provide a multi-platform application specific standard product (ASSP). This is especially advantageous for providing multi-platform devices for use in countries or applications where one or more standards may be employed.

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  • Configurable communication integrated circuit

    Issued US 6,957,283

    The present invention is a programmable integrated circuit that can be used to handle different communication specifications. In one embodiment, the integrated circuit contains at least two physical layer modules, a media independent interface and a media access control module. The physical layer modules are preferably fixed logic components embedded in programmable logic fabric. In another embodiment, the integrated circuit contains a physical layer module and at least two media access control…

    The present invention is a programmable integrated circuit that can be used to handle different communication specifications. In one embodiment, the integrated circuit contains at least two physical layer modules, a media independent interface and a media access control module. The physical layer modules are preferably fixed logic components embedded in programmable logic fabric. In another embodiment, the integrated circuit contains a physical layer module and at least two media access control modules. The physical layer module is preferably a fixed logic component embedded in programmable logic fabric.

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  • Programmable logic device for wireless local area network

    Issued EU 20050084076

    Method and apparatus for a wireless local area network programmable logic device is described. More particularly, a field programmable gate array (FPGA) is coupled to memory having programming instructions for configuring the FPGA with a medium access layer selected from more than one type of medium access layers. A physical layer is hardwired or embedded on the FPGA, or a separate integrated circuit for the physical layer is used. Additionally, the memory comprises programming instructions for…

    Method and apparatus for a wireless local area network programmable logic device is described. More particularly, a field programmable gate array (FPGA) is coupled to memory having programming instructions for configuring the FPGA with a medium access layer selected from more than one type of medium access layers. A physical layer is hardwired or embedded on the FPGA, or a separate integrated circuit for the physical layer is used. Additionally, the memory comprises programming instructions for a baseband controller, and may include programming instructions for a baseband processor, for configuring the FPGA in accordance therewith. In this manner, a single physical layer may be used with an FPGA to provide a multi-platform application specific standard product (ASSP). This is especially advantageous for providing multi-platform devices for use in countries or applications where one or more standards may be employed.

    Other inventors
    • Krishna Rangasayee
    See patent

  • Configurable communication integrated circuit

    Issued EU 20030023762

    The present invention is a programmable integrated circuit that can be used to handle different communication specifications. In one embodiment, the integrated circuit contains at least two physical layer modules, a media independent interface and a media access control module. The physical layer modules are preferably fixed logic components embedded in programmable logic fabric. In another embodiment, the integrated circuit contains a physical layer module and at least two media access control…

    The present invention is a programmable integrated circuit that can be used to handle different communication specifications. In one embodiment, the integrated circuit contains at least two physical layer modules, a media independent interface and a media access control module. The physical layer modules are preferably fixed logic components embedded in programmable logic fabric. In another embodiment, the integrated circuit contains a physical layer module and at least two media access control modules. The physical layer module is preferably a fixed logic component embedded in programmable logic fabric.

    Other inventors
    • Krishna Rangasayee
    See patent

Languages

  • English

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  • Hindi

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  • Punjabi

    Professional working proficiency

  • Arabic

    Limited working proficiency

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