Priya Gupta

**Unlock Your VLSI Potential: Semicon Technolabs Live Demo on Analog Layout – Nov 10th, 2024 at 10 AM IST** The VLSI industry is growing at an unprecedented pace, but there's a significant gap in the availability of skilled professionals to meet the demand for cutting-edge semiconductor technologies. To help bridge this gap, **Semicon Technolabs** is hosting a **live demo on Analog Layout**a crucial skill in the VLSI design process on **November 10th, 2024**, at **10:00 AM IST**. This live demo is designed to provide students, recent graduates, and professionals with the hands-on knowledge they need to excel in the world of analog IC design. Whether you’re looking to get into the VLSI industry or expand your skillset, this session will provide you with a deeper understanding of analog layout design techniques and how to apply them in real-world scenarios. **What You’ll Learn in the Live Demo:** - **Introduction to Analog Layout**: Gain a foundational understanding of analog IC design and the importance of layout in the VLSI process. - **Key Concepts and Techniques**: Explore critical analog layout techniques such as transistor sizing, device matching, and parasitic extraction. - **Tools of the Trade**: Get exposure to industry-standard EDA tools used in analog layout design. - **Practical Tips & Best Practices**: Learn how to optimize layouts for PPA while adhering to design rules. - **Career Opportunities in Analog Layout**: Understand how mastering analog layout can help you stand out in the competitive job market. **Why Should You Enroll?** 1. **Bridging the Industry Skill Gap**: The VLSI sector is booming, but there's a significant shortage of skilled professionals in specialized areas like analog layout. This demo will equip you to understand the industry needs. 2. **Practical Learning**: Unlike typical classroom sessions, this demo will focus on practical techniques that you can apply to real-world design challenges. Learn by doing, not just by listening. 3. **Interactive Q&A with Experts**: After the demo, there will be an opportunity for you to ask questions directly to the experts at Semicon Technolabs. Get valuable insights into the industry and get answers to your specific queries. 4. **Kickstart Your VLSI Career**: If you are a student or recent graduate, this is a great way to make yourself more marketable to employers in the rapidly growing semiconductor industry. **Conclusion:** Semicon Technolabs is offering an invaluable opportunity for anyone looking to break into the VLSI industry. Analog layout design is a key area of expertise, and mastering it could be the key to unlocking numerous career opportunities. Registration Form- https://lnkd.in/efJSrE8K Subscribe to Our YouTube Channel- https://lnkd.in/e6Ka_j_y #FreeDemo #DEMO2024 #SemiconTraining #engineeringcareers #EngineeringGraduates #Graduates #graduates2024 #vlsi #vlsidesign #techfuture #CareerInTech #BTech #MTechGraduates

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I am thrilled to announce that our paper titled "TVTAC: Triple Voltage Threshold Approximate Cache For Energy Harvesting Nonvolatile Processors" has been accepted for publication in the prestigious IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) Journal. This work represents a significant step forward in designing energy-efficient cache systems for nonvolatile processors, and I am eager to share our findings at IUST CPS Lab (http://cps.iust.ac.ir) with the broader research and engineering community. TVTAC introduces a novel cache management scheme designed to enhance the forward progress and energy efficiency of nonvolatile processors (NVPs) used in energy-harvesting systems. These systems are increasingly prevalent in IoT devices, wearables, and medical implants due to their ability to operate on intermittent power supplies. For those interested in exploring the details of our research, the paper is now accessible at: IEEE Xplore Digital Library (https://lnkd.in/dKQcx7fp). I would like to express my profound gratitude to my esteemed co-authors, Mohammad Hosseininia and Arash Salahvarzi, whose insightful contributions and dedicated collaboration were instrumental in the success of our study. #IEEE #EnergyHarvesting #NonvolatileProcessors #Research #Innovation

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Ever wonder how 2 state variable will work in Systemverilog? Find out more on my new blog where I have explained with it's usage in associative array. #verification #ASIC #Systemverilog #UVM

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What are the reasons for routing congestion 📢 Inefficient floorplan 📢 Macro placement or macro channels is not proper. 📢 Placement blockages not given 📢 No Macro to Macro channel space given. 📢 High cell density 📢 High local utilization 📢 High number of complex cells like AOI/OAI cells which has more pin count are placed together. 📢 Placement of std cells near macros 📢 Logic optimization is not properly done. 📢 Pin density is more on edge of block 📢 Buffers added too many while optimization 📢 IO ports are crisscrossed, it needs to be properly aligned in order. What are the different methods to reduce congestion. 📢 Review the floorplan/macro placements according to the block size and 📢 port placement. 📢 Add proper placement blockages in channels and around the macro boundaries. 📢 Reduce the local density using the percentage utilization/density screens. 📢 Cell padding is applied for high pin density cells, like AOI/OAI. 📢 Check and reorder scan chain if needed. 📢 Run the congestion driven placement with high effort. 📢 Check the power network is proper and on routing tract. If it is not on track, adjacent routing tracts may not be used, so it might lead to congestion

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MosChip® selects Cadence tools for the design of HPC Processor “AUM” for C-DAC 💡👇 Hyderabad, India -- December 11, 2024 — MosChip® Technologies selects Cadence 5nm EDA tools for the design of the High-Performance Computing (HPC) Processor “AUM” for C-DAC.   MosChip® Technologies is the first fabless semiconductor company publicly traded in India. It has over twenty-five years of experience designing products and SoCs with a vision to be a preferred partner for technology and excellence throughout the SoC development cycle. MosChip® also provides Turnkey ASIC solutions using advanced EDA tools and proven design flow. Supported by a focused team of domain experts, MosChip® delivers technologically advanced solutions for various applications spanning Computing, Automotive, Consumer Electronics, Telecommunications, Industrial Automation, Healthcare, etc.   As India’s demand for data processing and high-speed computing increases, the AUM processor represents a significant milestone in supporting next-generation applications across industries. MosChip® will utilize Cadence EDA tools for linting, verification, synthesis, PNR implementation, timing, and PNR signoff in the AUM processor project. Moreover, MosChip® has used the Cadence tool suite on multiple customer SoCs that progressed to volume production. Read more here: https://lnkd.in/dSZESK5m Mustaqh Ali Shaik Yash Dhagat Srilakshmi Simhadri Jayashankar Narayanankutty

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Hi All, Our PCIe course will available at price of INR 4999/- only from 31st October to 8th November. Garb the Offer if you are looking to skill and ramp yourself in PCIe. Along with full video course we will also give other supporting study material, and will assign one mentor with whom you can ask your queries related to PCIe. Visit the site : bazinga-vlsi.com For Complete PCIE Course Content click here: https://lnkd.in/gBp-DQDB Here's the link to Sample Video : [PCIE Session 3 : PCIe Configuration Overview] https://lnkd.in/gMGiuDaa Students from ‘Electronics’ and ‘Computer Science’ background, who are looking to build a career in VLSI Industry, adding the PCIe skillset to your resume is going to put you much ahead of the competition. Prerequisite: Should have understanding of Digital Electronics !!! If you are working professional in VLSI Industry, (Design Engineer, Verification Engineers, Firmware Engineers, Embedded Engineers), having PCIe skillet is definitely going boost your professional growth, and has high potential to fuel your earning potential. For Queries Ping me @ +91 8867739709 hashtag hashtag #pcie hashtag hashtag #pcietraining hashtag hashtag #learning

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Hi All, Our PCIe course will available at price of INR 4999/- only from 31st October to 8th November. Garb the Offer if you are looking to skill and ramp yourself in PCIe. Along with full video course we will also give other supporting study material, and will assign one mentor with whom you can ask your queries related to PCIe. Visit the site : bazinga-vlsi.com For Complete PCIE Course Content click here: https://lnkd.in/gBp-DQDB Here's the link to Sample Video : [PCIE Session 3 : PCIe Configuration Overview] https://lnkd.in/gMGiuDaa Students from ‘Electronics’ and ‘Computer Science’ background, who are looking to build a career in VLSI Industry, adding the PCIe skillset to your resume is going to put you much ahead of the competition. Prerequisite: Should have understanding of Digital Electronics !!! If you are working professional in VLSI Industry, (Design Engineer, Verification Engineers, Firmware Engineers, Embedded Engineers), having PCIe skillet is definitely going boost your professional growth, and has high potential to fuel your earning potential. For Queries Ping me @ +91 8867739709 hashtag #pcie hashtag #pcietraining hashtag #learning

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Indian semiconductor ecosystem is thriving. With big push from government, an excellent corporate-govt partnership and an awakened indian market who is valuing “make in India , made for India , made by Indians” movement. A great energy and synergy everywhere. Follow VLSI Society of India (VSI)

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🟢 Synopsys's $35B Ansys Acquisition Under UK Regulatory Scrutiny The UK's Competition and Markets Authority (CMA) has launched an early-stage inquiry into Synopsys's $35 billion acquisition of Ansys. This move enables stakeholders to provide feedback on the proposed transaction, announced in January 2024. The merger aims to combine Synopsys's chip design software prowess with Ansys's simulation capabilities, establishing a robust chip design and simulation entity. While the merger is anticipated to enhance development processes, concerns about potential market dominance have arisen. Apart from the US Federal Trade Commission, European and Chinese regulators are expected to scrutinize the deal due to the substantial market impact resulting from the consolidation of two key players in the semiconductor design and simulation software sector. The regulatory spotlight on the Synopsys-Ansys deal mirrors the increasing global scrutiny of major tech mergers. With the semiconductor industry growing in strategic importance, regulators are vigilant about preventing consolidation from hindering competition and innovation. The investigations' outcomes could significantly influence the trajectory of chip design and simulation technologies. Synopsys Inc Ansys

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🔴 🔴 🔴 For all future chip designers and those interested in joining the Indian semiconductor industry: I highly recommend watching this must-see series that offers a deep dive into the history and evolution of chip technology. Watch with patience and curiosity, as these videos will give you an understanding of how the idea of multi-functional chips came into existence. 👉 It all began with the inefficiencies of targeting during World War II and the early stages of the Cold War. Back then, military forces struggled with precision—only about 20% of bombs could hit within a 1000m range of their intended targets. This lack of accuracy pushed the need for better technology, which eventually led to incredible innovations in electronics, including semiconductors. 👉The series also touches upon how Russia’s strategy of trying to copy Western technology throughout the Cold War often led to failure. While copying worked in some cases, Russia lagged behind in innovation, especially in microelectronics and chip design. On the other hand, the U.S. was rapidly advancing in chip-making technology, laying the groundwork for the modern semiconductor industry. 👉Japan also played a pivotal role by taking U.S. technology and refining it. In the 1980s, Japan became a leader in manufacturing efficiency and mass production, particularly in memory chips like DRAM. Their ability to scale production and create high-quality products transformed the global electronics industry. 👉So far, I’ve watched 5 videos in this series, and I plan to complete the rest by the end of this week. These lectures, delivered by Professor Rajesh Zele from IIT Bombay, provide valuable insights into how these technological advancements shaped the world we live in today. For anyone looking to understand the history of semiconductors and how they became the backbone of modern technology, this series is a must-watch! #chipstory #Rajeshzele #iitbombay https://lnkd.in/eixng-KJ

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Our project on "Cross-Layer Design Automation for In-Memory Analog Computing" has received funding from the Software & Hardware Foundation (SHF) program at the National Science Foundation (NSF). Special thanks to my collaborator, Dr. Jason Bakos, and a big shoutout to my amazing students for all their contributions especially Md Hasibul Amin, Mohammed Elbtity, and Brendan Reidy who helped with collecting the preliminary results for the proposal! Stay tuned for more updates!! #inmemorycomputing #neuromorphic

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🔍 CMOS Technology and Its Significance 🔍 As someone passionate about VLSI design, I’ve always been fascinated by CMOS technology. Complementary Metal-Oxide-Semiconductor (CMOS) is a cornerstone in modern electronics, and its impact on the industry cannot be overstated. CMOS technology is the driving force behind the majority of digital circuits today. Its ability to provide high noise immunity and low static power consumption makes it the go-to choice for everything from microprocessors to memory chips. 🌟 Here’s what makes CMOS so significant: Power Efficiency: CMOS circuits are designed to consume minimal power when idle. This efficiency is crucial for battery-operated devices and has revolutionized the way we approach portable electronics. 📱 High Speed: The technology allows for rapid switching between the on and off states, which translates to faster processing speeds. This is a major reason why CMOS is integral to high-performance computing. ⚡ Scalability: As technology advances, CMOS allows for scaling down of transistors, which means we can pack more functionality into smaller chips. This scalability is key to developing smaller, more powerful devices. 🧩 Reliability: CMOS technology is known for its reliability in various environmental conditions. This makes it ideal for both consumer electronics and critical systems in aerospace and automotive industries. 🚀 I remember diving into CMOS during my studies—it was a game-changer in understanding how digital circuits operate efficiently. The more I explored, the more I realized how pivotal CMOS is in shaping modern electronics. What are your thoughts on CMOS technology? How has it impacted your work or studies? Let’s discuss in the comments! 👇 #CMOS #VLSI #Electronics #Technology #Engineering #DigitalDesign #PowerEfficiency #Microprocessors #Innovation #TechTrends

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A low-cost FPGA for high-speed MIPI C-PHY & D-PHY – Introducing Gowin Semiconductor Corp’s Arora-V GW5AT-15 ipXchange rarely comes across a disruptive FPGA to share with our members, but at Sensors Converge 2024, we caught up with David Grugett from GOWIN Semiconductor, who have just announced the new Arora-V GW5AT-15 FPGA, with 15,120 logic elements, inbuilt memory, and high-speed SerDes interfaces supporting 4K video at up to 120 fps! Learn more and apply to evaluate this technology on the ipXchange website: https://lnkd.in/eXYkuZrw Keep designing! #embedded #FPGA #MIPICPHY #MIPIDPHY #MIPI #electronics #electronicsengineering #disruptivetechnology #semiconductor #lowcostFPGA #Verilog #automotiveFPGA #automotive #automotiveelectronics #consumerelectronics #4KvideoFPGA #4Kvideo #SerDes 

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Interesting read

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🔶 MOSFET EVOLUTION 🔶  Planar MOSFET ➡ FinFET ➡ GAA(Gate All Around) 👉 The foundation of modern electronics is the CMOS transistor.  🔹 The innovations in CMOS technology have been obtained through continuous downscaling for higher density, better performance, and low power consumption, leading to detrimental short-channel effects. 👉 Planar MOSFETs encountered tough challenges in the nanometer space, so FinFETs emerged as their replacements. FinFET stands for a fin-shaped field-effect transistor:     🔹 Fin because it has a fin-shaped body – the silicon fin that forms the transistor’s main body distinguishes it.      🔹 Field-effect because an electric field controls the conductivity of the material. 🧐 Why Use FinFET Devices in Place of MOSFETs? 🔸 Increasing computational power implies increasing computational density. More transistors are required to achieve this, which leads to larger chips. However, for practical reasons, it is crucial to keep the area about the same. 🔸 One way of achieving more computational power is by shrinking the transistor’s size. But as the transistor’s dimensions decrease, planar MOSFETs display objectionable short-channel effects. 🔸 Shrinking the gate length (Lg) below 90 nm produces a significant leakage current, and below 28 nm, the leakage is excessive, rendering the transistor useless. 🔸 Another way to increase computational power is by changing the materials used for manufacturing the chips, but it may not be suitable from an economic standpoint. ✅ FinFET devices display superior short-channel behavior, have considerably lower switching times, and higher current density than conventional MOSFET technology. 👉 FinFET will not be useful beyond 5nm, as it will not have enough electrostatic control, requiring new architectures for the transistors. ✅ The gate-all-around (GAA) transistor emerges as the successor to FinFET for significantly scaled process nodes. The GAA structure provides the most significant capacitive coupling between the gate and the channel. Join VLSI Jobs : Whatsapp Channel : https://lnkd.in/dhrqNMgv Download VLSI FOR ALL Community App : https://lnkd.in/dB_QDcHT FREE Mentorship : https://wa.me/919643070368 Apple Users App Link : https://lnkd.in/dA_7YmYJ Write us on [email protected] Follow VLSI FOR ALL Pvt Limited Source : Pooja Kumawat #mosfet #gaa #fet #vlsi #vlsidesign #transistor #cmos credit: https://lnkd.in/dqi5pgdx

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#Day9 of #21DaysofRTL Successfully solved a problem on the QuickSilicon platform involving the design and implementation of a Binary-to-Gray Code Converter. This task required in-depth knowledge of digital logic, binary number systems, and Verilog HDL. ___________________________________________________________________________________ Design and verify a parameterized binary to gray code converter Interface Definition The module should have the following interface: module day9 #( parameter VEC_W = 4 )( input wire[VEC_W-1:0] bin_i, output wire[VEC_W-1:0] gray_o ___________________________________________________________________________________ This experience strengthens my commitment to pursuing a career as a Design and Verification Engineer in the semiconductor industry

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🌟 Building India’s Semiconductor Workforce 🌟 As India steps up to become a global hub for semiconductor innovation, the need for a highly skilled and industry-ready workforce has never been more critical. Skilling programs focused on design, verification, and specialized domains like SoC Verification and DFT are the key to driving this transformation. This article highlights how talent development initiatives, practical training, and industry-aligned curriculums are bridging the talent gap and supporting India’s semiconductor mission. At Semi Design, we are proud to contribute to this mission with: ✅ Design & Verification Training Programs ✅ SoC Verification and DFT Specializations ✅ Hands-on RTL to GDSII Training ✅ Personalized mock interviews, assessments, and industry-relevant projects Led by experts with 20+ years of experience, our programs are designed to prepare you for real-world challenges in semiconductor design and verification. Let’s work together to build a thriving semiconductor ecosystem in India. 🚀 👉 Read the full article here: Talent Development and Skilling Programs: Building India’s Semiconductor Workforce #Semiconductor #DesignAndVerification #SoCVerification #DFT #WorkforceDevelopment #SemiDesign #Innovation

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🚀 Analog VLSI: The Silent Powerhouse Driving Quantum Computing 🧑‍💻 In the rapidly evolving landscape of Quantum Computing 🌐, where qubits, entanglement, and superposition are the buzzwords, there's an unsung hero that's playing a pivotal role—Analog VLSI. Let's delve into how Analog VLSI is contributing to this cutting-edge technology and why it's indispensable! 🔍 #1️⃣ The Foundation of Precision Quantum computing relies on the manipulation of quantum states, which demands ultra-precise control over signals. 🎛️ Analog VLSI circuits excel in generating and processing continuous signals with high fidelity, enabling the precise control needed to manipulate qubits effectively. Without this precision, the delicate quantum states could easily be disrupted, leading to computational errors. ⚠️ #2️⃣ Bridging the Classical-Quantum Divide One of the challenges in quantum computing is the interface between classical and quantum domains. Analog VLSI provides a seamless bridge 🌉 by enabling efficient data conversion and signal processing. Through high-speed Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs), it translates quantum information into classical data formats, allowing for effective monitoring, control, and error correction in quantum systems. 🖥️ #3️⃣ Power Efficiency at Its Best In quantum computing, maintaining qubit coherence requires low temperatures, often near absolute zero ❄️. This poses significant challenges in power management. Analog VLSI circuits are inherently power-efficient, ensuring minimal thermal noise and heat generation. This efficiency is crucial in maintaining the delicate balance required for qubits to function properly over extended periods. 🕒 #4️⃣ Real-Time Signal Processing Quantum computers require real-time signal processing to maintain qubit coherence and perform operations swiftly. Analog VLSI, with its fast response times and low-latency signal processing capabilities ⏱️, is key to ensuring that quantum operations are executed with the speed and accuracy required for practical applications. #5️⃣ Scalability and Integration As quantum computing scales up, the integration of numerous qubits and control circuits becomes complex. Analog VLSI offers high-density integration capabilities, allowing for the compact design of quantum processors. This integration is critical in developing scalable quantum systems that can handle more qubits and deliver higher computational power. 📈 #6️⃣ The Future Outlook The fusion of Analog VLSI with quantum computing technology is paving the way for new frontiers in computing power and efficiency. As we advance toward practical quantum computers, the role of Analog VLSI will only grow more prominent, becoming the backbone that supports the next wave of technological breakthroughs 🌍. Follow Soumick Majumdar for more such technical content. Happy Connecting !!! #QuantumComputing #AnalogVLSI #VLSI #iiitb #gate #gate2025 #innovation

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