Gian Marco Iodice

Some interesting thoughts on the RISC-V specification from someone with huge experience in ISA specifications: https://lnkd.in/ekG2cvHU I strongly agree with Alastair, there is much that could be improved in the RISC-V specification.

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The latest report from ABI Research looks at how embedded chipset vendors are increasingly prioritising Neural Processing Units (NPUs) for IoT applications due to their efficient handling of neural network workloads. Find out more 'NPUs are being prioritised for IoT Applications, says ABI Research'👇 https://bit.ly/4fgOP0R #iotinsider #IoT #engineer #tech #technology

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Next up in our Whiteboard video series Jamie Melling explains the scenarios in which Virtual Memory is needed and how to implement it in your RISC-V project.

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Came across this brilliant article today on the highly relevant topic of low power FPGA design considerations written by none other than Lance Harvie Bsc (Hons). Highly recommend a read and well done Lance! https://lnkd.in/gFPgs6qi

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What is an FPGA? Do I need to use them? Will FPGA cards accelerate my electronic trading strategy? ⚡ In this article, CTO James Lupton and CRO Ciaran Kennedy answer your questions about FPGA. 🔗Tap to read the full article: https://loom.ly/UR4j11s

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In this episode of the RISC-V series by Axiomise, we discuss coverage for formal verification and RISC-V. Tune in to find out how formal verification based testbenches should be signed off to gain assurance and verify beyond doubt that you're done. https://lnkd.in/eBKNVtAJ #coverage #socs #formalverification #riscv #semiconductors #icdesign #axiomise #verificationbeyonddoubt #fpga #asics

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In case you missed it, on Day One at DAC, Nitin Dahad of EE Times delved into EDA, tools, support for designing heterogeneous systems using chiplets and advanced packaging, and AI using RISC-V. Nitin first interviewed Shankar Krishnamoorthy, the general manager of Synopsys's EDA business. He discussed the convergence of silicon and systems, multi-die chiplet designs, and how EDA must address them.  Then Jim Keller, CEO of Tenstorrent, discussed his keynote, RISC-V, and where his company fits in the AI chip development race, KH Lee, president of Faraday USA, spoke with Nitin Dahad about designing AI chips and arm-based chaplet designs and the plan to build them using the Intel 18A process. Finally, Mike Wishart, CEO of efabless, described how his company enables custom chip design for just $10,000 and the 40 completed product designs.  https://lnkd.in/g25rpp9y #ai #chiplets #arm #risc-v #eda #multidie #advancedpackaging #heterogeneous

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🌎 According to Omdia, RISC-V processors will capture nearly a quarter of the global market by 2030. Join us at the RISC-V Summit Europe, where Edward Wilford from Omdia will discuss how rising intelligence across various sectors will drive RISC-V's growth. #RISCV #RISCVeverywhere #RISCVSummit

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Next up in our Whiteboard video series Jamie Melling explains the scenarios in which Virtual Memory is needed and how to implement it in your RISC-V project.

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According to XDA’s Elliot Alexander, RISC-V is subtly transforming the silicon market by fostering competitive innovation. Elliot highlighted the high entry barriers typical in chip design, explaining that RISC-V’s flexibility “makes innovation cheaper and faster,” which is why the open standard is seeing so much traction. Read more below.

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Try our Integrated Logic Analyzer! It is easy to use. https://lnkd.in/d-RpwA6x #fpga #GateMate #CologneChip #embeddedsystem #engineering #electronics #embeddedsoftware #debugging

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REGISTER: https://lnkd.in/eiymyNgU This workshop will cover common gotchas and roadblocks engineers commonly face when both implementing FPGA designs and bringing up PCBs for the first time. #fpga #debugging #hardwaredebugging #amd #xilinx #vivado

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In this paper we have shown the implementation of the Bitmanip extension support in application class RISC-V processor (CVA6) and evaluated the ASIC 294 and FPGA synthesis data, Linux code size and Dhrystone benchmark results. Read the full paper here: https://lnkd.in/dkNcxjMy

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Helpful Technical Paper on RISC-V Bit Manipulation evaluation and performance tested at our #OpenHW #CVA6 core by 10xEngineers #riscv #riscveverywhere #semiconductor

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“Few companies have made a larger impact in the RISC-V world than SiFive.” All About Circuits discusses the new SiFive Performance P870-D datacenter processor and how this product balances both performance and power. Read more: https://hubs.la/Q02LtCQK0 #RISCV #NoLimits

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ϕEng32/64 supports vector operations by augmenting the existing scalar instructions with four instruction prefixes. This is a natural outgrowth to support ϕPPL which is unique in extending scalar operators to also serve as vector operators when arrays and vectors of matching dimensions are used as operands. Processors such as RISC-V (using RV32I) are scalar processors. They must use loops to iterate through vector elements for vector operations. This brings up a situation where code density of two processor architectures can be compared in two ways. One is to compare the overall sizes of their programs. This is what I am calling PSCD (Program Size Code Density). For an objective comparison between the two architectures where one contains a looping algorithm and the other does not, you have to total the sizes of all of the instructions that are executed. That means you must count all of the instructions in the loop as many times as the loop is executed. This is what I am calling EPCD or Execution Path Code Density. I recently wrote two programs that simply add two vectors together to produce a third vector. In ϕPPL the code looks like this: [8]ut: A,B⇐〈0,1,2,3,4,5,6,7〉,C⇐〈1,2,3,4,5,6,7,8〉; A ⇐ B + C; The first line is only for reference. The second was used for coding comparison. A, B and C are all vectors of eight elements, each of which is an unsigned 24-bit integer. I wrote a short code sequence in ϕEng32 assembly which came to only 16 bytes in size. This is its PSCD. Since each instruction only executes once, it is also its EPCD. I also wrote a RISC-V program that was 60 bytes long which is its PSCD. I had to add looping control as well as the code that was contained within the loop. Adding up all of the code size for every time an instruction was executed, it came to 452 byes. The relative code density for PSCD was about 26.7% while it was only about 3.5% for the EPCD. In other words, the size of the code that had to be executed by RISC-V was over 28× that needed for ϕEng32! That's an astounding difference. #computers #electronics #programming #RISC #CISC #ϕEng32 #ϕPPL

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'Codasip opens up SDK for CHERI protection on RISC-V chips' - Check out the article from The Register discussing how we are donating the SDK we developed to the CHERI Alliance.

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'Codasip opens up SDK for CHERI protection on RISC-V chips' - Check out the article from The Register discussing how we are donating the SDK we developed to the CHERI Alliance.

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How is running AI locally different from using the cloud? Listen to this episode of the Technically Speaking podcast with Intel’s Robert Hallock to discover the added benefits of the Intel #AIPC with #IntelCoreUltra. #Intel #IntelvPro https://bit.ly/3yjbQzD

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