Mr. Huang got his Ph. D. in 1982 in the area of logic synthesis. He was the co-founder of Gateway Design Automation, Inc. with Dr. Prabhu Goel . Huang and Phil Moorby worked on the language definition and first implementation of Verilog. Huang is partially responsible for Verilog being a synthesizable language.
Since then, he has been working in fault simulation, timing verification, and synthesis areas. He was responsible for Cadence’s RTL synthesis effort for several years and eventually led the whole synthesis project. He left Cadence and started Avery at 1998.
