clang  3.7.0
Targets.cpp
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1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/TargetParser.h"
31 #include <algorithm>
32 #include <memory>
33 using namespace clang;
34 
35 //===----------------------------------------------------------------------===//
36 // Common code shared among targets.
37 //===----------------------------------------------------------------------===//
38 
39 /// DefineStd - Define a macro name and standard variants. For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 /// when in GNU mode.
42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43  const LangOptions &Opts) {
44  assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45 
46  // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47  // in the user's namespace.
48  if (Opts.GNUMode)
49  Builder.defineMacro(MacroName);
50 
51  // Define __unix.
52  Builder.defineMacro("__" + MacroName);
53 
54  // Define __unix__.
55  Builder.defineMacro("__" + MacroName + "__");
56 }
57 
58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59  bool Tuning = true) {
60  Builder.defineMacro("__" + CPUName);
61  Builder.defineMacro("__" + CPUName + "__");
62  if (Tuning)
63  Builder.defineMacro("__tune_" + CPUName + "__");
64 }
65 
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
69 
70 namespace {
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
73 protected:
74  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75  MacroBuilder &Builder) const=0;
76 public:
77  OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78  void getTargetDefines(const LangOptions &Opts,
79  MacroBuilder &Builder) const override {
80  TgtInfo::getTargetDefines(Opts, Builder);
81  getOSDefines(Opts, TgtInfo::getTriple(), Builder);
82  }
83 
84 };
85 } // end anonymous namespace
86 
87 
89  const llvm::Triple &Triple,
90  StringRef &PlatformName,
91  VersionTuple &PlatformMinVersion) {
92  Builder.defineMacro("__APPLE_CC__", "6000");
93  Builder.defineMacro("__APPLE__");
94  Builder.defineMacro("OBJC_NEW_PROPERTIES");
95  // AddressSanitizer doesn't play well with source fortification, which is on
96  // by default on Darwin.
97  if (Opts.Sanitize.has(SanitizerKind::Address))
98  Builder.defineMacro("_FORTIFY_SOURCE", "0");
99 
100  if (!Opts.ObjCAutoRefCount) {
101  // __weak is always defined, for use in blocks and with objc pointers.
102  Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
103 
104  // Darwin defines __strong even in C mode (just to nothing).
105  if (Opts.getGC() != LangOptions::NonGC)
106  Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
107  else
108  Builder.defineMacro("__strong", "");
109 
110  // __unsafe_unretained is defined to nothing in non-ARC mode. We even
111  // allow this in C, since one might have block pointers in structs that
112  // are used in pure C code and in Objective-C ARC.
113  Builder.defineMacro("__unsafe_unretained", "");
114  }
115 
116  if (Opts.Static)
117  Builder.defineMacro("__STATIC__");
118  else
119  Builder.defineMacro("__DYNAMIC__");
120 
121  if (Opts.POSIXThreads)
122  Builder.defineMacro("_REENTRANT");
123 
124  // Get the platform type and version number from the triple.
125  unsigned Maj, Min, Rev;
126  if (Triple.isMacOSX()) {
127  Triple.getMacOSXVersion(Maj, Min, Rev);
128  PlatformName = "macosx";
129  } else {
130  Triple.getOSVersion(Maj, Min, Rev);
131  PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
132  }
133 
134  // If -target arch-pc-win32-macho option specified, we're
135  // generating code for Win32 ABI. No need to emit
136  // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
137  if (PlatformName == "win32") {
138  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
139  return;
140  }
141 
142  // Set the appropriate OS version define.
143  if (Triple.isiOS()) {
144  assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
145  char Str[6];
146  Str[0] = '0' + Maj;
147  Str[1] = '0' + (Min / 10);
148  Str[2] = '0' + (Min % 10);
149  Str[3] = '0' + (Rev / 10);
150  Str[4] = '0' + (Rev % 10);
151  Str[5] = '\0';
152  Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
153  Str);
154  } else if (Triple.isMacOSX()) {
155  // Note that the Driver allows versions which aren't representable in the
156  // define (because we only get a single digit for the minor and micro
157  // revision numbers). So, we limit them to the maximum representable
158  // version.
159  assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
160  char Str[7];
161  if (Maj < 10 || (Maj == 10 && Min < 10)) {
162  Str[0] = '0' + (Maj / 10);
163  Str[1] = '0' + (Maj % 10);
164  Str[2] = '0' + std::min(Min, 9U);
165  Str[3] = '0' + std::min(Rev, 9U);
166  Str[4] = '\0';
167  } else {
168  // Handle versions > 10.9.
169  Str[0] = '0' + (Maj / 10);
170  Str[1] = '0' + (Maj % 10);
171  Str[2] = '0' + (Min / 10);
172  Str[3] = '0' + (Min % 10);
173  Str[4] = '0' + (Rev / 10);
174  Str[5] = '0' + (Rev % 10);
175  Str[6] = '\0';
176  }
177  Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
178  }
179 
180  // Tell users about the kernel if there is one.
181  if (Triple.isOSDarwin())
182  Builder.defineMacro("__MACH__");
183 
184  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
185 }
186 
187 namespace {
188 // CloudABI Target
189 template <typename Target>
190 class CloudABITargetInfo : public OSTargetInfo<Target> {
191 protected:
192  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
193  MacroBuilder &Builder) const override {
194  Builder.defineMacro("__CloudABI__");
195  Builder.defineMacro("__ELF__");
196 
197  // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
198  Builder.defineMacro("__STDC_ISO_10646__", "201206L");
199  Builder.defineMacro("__STDC_UTF_16__");
200  Builder.defineMacro("__STDC_UTF_32__");
201  }
202 
203 public:
204  CloudABITargetInfo(const llvm::Triple &Triple)
205  : OSTargetInfo<Target>(Triple) {
206  this->UserLabelPrefix = "";
207  }
208 };
209 
210 template<typename Target>
211 class DarwinTargetInfo : public OSTargetInfo<Target> {
212 protected:
213  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
214  MacroBuilder &Builder) const override {
215  getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
216  this->PlatformMinVersion);
217  }
218 
219 public:
220  DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
221  this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
222  this->MCountName = "\01mcount";
223  }
224 
225  std::string isValidSectionSpecifier(StringRef SR) const override {
226  // Let MCSectionMachO validate this.
227  StringRef Segment, Section;
228  unsigned TAA, StubSize;
229  bool HasTAA;
230  return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
231  TAA, HasTAA, StubSize);
232  }
233 
234  const char *getStaticInitSectionSpecifier() const override {
235  // FIXME: We should return 0 when building kexts.
236  return "__TEXT,__StaticInit,regular,pure_instructions";
237  }
238 
239  /// Darwin does not support protected visibility. Darwin's "default"
240  /// is very similar to ELF's "protected"; Darwin requires a "weak"
241  /// attribute on declarations that can be dynamically replaced.
242  bool hasProtectedVisibility() const override {
243  return false;
244  }
245 };
246 
247 
248 // DragonFlyBSD Target
249 template<typename Target>
250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
251 protected:
252  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
253  MacroBuilder &Builder) const override {
254  // DragonFly defines; list based off of gcc output
255  Builder.defineMacro("__DragonFly__");
256  Builder.defineMacro("__DragonFly_cc_version", "100001");
257  Builder.defineMacro("__ELF__");
258  Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
259  Builder.defineMacro("__tune_i386__");
260  DefineStd(Builder, "unix", Opts);
261  }
262 public:
263  DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
264  : OSTargetInfo<Target>(Triple) {
265  this->UserLabelPrefix = "";
266 
267  switch (Triple.getArch()) {
268  default:
269  case llvm::Triple::x86:
270  case llvm::Triple::x86_64:
271  this->MCountName = ".mcount";
272  break;
273  }
274  }
275 };
276 
277 // FreeBSD Target
278 template<typename Target>
279 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
280 protected:
281  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
282  MacroBuilder &Builder) const override {
283  // FreeBSD defines; list based off of gcc output
284 
285  unsigned Release = Triple.getOSMajorVersion();
286  if (Release == 0U)
287  Release = 8;
288 
289  Builder.defineMacro("__FreeBSD__", Twine(Release));
290  Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
291  Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
292  DefineStd(Builder, "unix", Opts);
293  Builder.defineMacro("__ELF__");
294 
295  // On FreeBSD, wchar_t contains the number of the code point as
296  // used by the character set of the locale. These character sets are
297  // not necessarily a superset of ASCII.
298  //
299  // FIXME: This is wrong; the macro refers to the numerical values
300  // of wchar_t *literals*, which are not locale-dependent. However,
301  // FreeBSD systems apparently depend on us getting this wrong, and
302  // setting this to 1 is conforming even if all the basic source
303  // character literals have the same encoding as char and wchar_t.
304  Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
305  }
306 public:
307  FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
308  this->UserLabelPrefix = "";
309 
310  switch (Triple.getArch()) {
311  default:
312  case llvm::Triple::x86:
313  case llvm::Triple::x86_64:
314  this->MCountName = ".mcount";
315  break;
316  case llvm::Triple::mips:
317  case llvm::Triple::mipsel:
318  case llvm::Triple::ppc:
319  case llvm::Triple::ppc64:
320  case llvm::Triple::ppc64le:
321  this->MCountName = "_mcount";
322  break;
323  case llvm::Triple::arm:
324  this->MCountName = "__mcount";
325  break;
326  }
327  }
328 };
329 
330 // GNU/kFreeBSD Target
331 template<typename Target>
332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
333 protected:
334  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
335  MacroBuilder &Builder) const override {
336  // GNU/kFreeBSD defines; list based off of gcc output
337 
338  DefineStd(Builder, "unix", Opts);
339  Builder.defineMacro("__FreeBSD_kernel__");
340  Builder.defineMacro("__GLIBC__");
341  Builder.defineMacro("__ELF__");
342  if (Opts.POSIXThreads)
343  Builder.defineMacro("_REENTRANT");
344  if (Opts.CPlusPlus)
345  Builder.defineMacro("_GNU_SOURCE");
346  }
347 public:
348  KFreeBSDTargetInfo(const llvm::Triple &Triple)
349  : OSTargetInfo<Target>(Triple) {
350  this->UserLabelPrefix = "";
351  }
352 };
353 
354 // Minix Target
355 template<typename Target>
356 class MinixTargetInfo : public OSTargetInfo<Target> {
357 protected:
358  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
359  MacroBuilder &Builder) const override {
360  // Minix defines
361 
362  Builder.defineMacro("__minix", "3");
363  Builder.defineMacro("_EM_WSIZE", "4");
364  Builder.defineMacro("_EM_PSIZE", "4");
365  Builder.defineMacro("_EM_SSIZE", "2");
366  Builder.defineMacro("_EM_LSIZE", "4");
367  Builder.defineMacro("_EM_FSIZE", "4");
368  Builder.defineMacro("_EM_DSIZE", "8");
369  Builder.defineMacro("__ELF__");
370  DefineStd(Builder, "unix", Opts);
371  }
372 public:
373  MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
374  this->UserLabelPrefix = "";
375  }
376 };
377 
378 // Linux target
379 template<typename Target>
380 class LinuxTargetInfo : public OSTargetInfo<Target> {
381 protected:
382  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
383  MacroBuilder &Builder) const override {
384  // Linux defines; list based off of gcc output
385  DefineStd(Builder, "unix", Opts);
386  DefineStd(Builder, "linux", Opts);
387  Builder.defineMacro("__gnu_linux__");
388  Builder.defineMacro("__ELF__");
389  if (Triple.getEnvironment() == llvm::Triple::Android) {
390  Builder.defineMacro("__ANDROID__", "1");
391  unsigned Maj, Min, Rev;
392  Triple.getEnvironmentVersion(Maj, Min, Rev);
393  this->PlatformName = "android";
394  this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
395  }
396  if (Opts.POSIXThreads)
397  Builder.defineMacro("_REENTRANT");
398  if (Opts.CPlusPlus)
399  Builder.defineMacro("_GNU_SOURCE");
400  }
401 public:
402  LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
403  this->UserLabelPrefix = "";
404  this->WIntType = TargetInfo::UnsignedInt;
405 
406  switch (Triple.getArch()) {
407  default:
408  break;
409  case llvm::Triple::ppc:
410  case llvm::Triple::ppc64:
411  case llvm::Triple::ppc64le:
412  this->MCountName = "_mcount";
413  break;
414  }
415  }
416 
417  const char *getStaticInitSectionSpecifier() const override {
418  return ".text.startup";
419  }
420 };
421 
422 // NetBSD Target
423 template<typename Target>
424 class NetBSDTargetInfo : public OSTargetInfo<Target> {
425 protected:
426  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
427  MacroBuilder &Builder) const override {
428  // NetBSD defines; list based off of gcc output
429  Builder.defineMacro("__NetBSD__");
430  Builder.defineMacro("__unix__");
431  Builder.defineMacro("__ELF__");
432  if (Opts.POSIXThreads)
433  Builder.defineMacro("_POSIX_THREADS");
434 
435  switch (Triple.getArch()) {
436  default:
437  break;
438  case llvm::Triple::arm:
439  case llvm::Triple::armeb:
440  case llvm::Triple::thumb:
441  case llvm::Triple::thumbeb:
442  Builder.defineMacro("__ARM_DWARF_EH__");
443  break;
444  }
445  }
446 public:
447  NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
448  this->UserLabelPrefix = "";
449  this->MCountName = "_mcount";
450  }
451 };
452 
453 // OpenBSD Target
454 template<typename Target>
455 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
456 protected:
457  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
458  MacroBuilder &Builder) const override {
459  // OpenBSD defines; list based off of gcc output
460 
461  Builder.defineMacro("__OpenBSD__");
462  DefineStd(Builder, "unix", Opts);
463  Builder.defineMacro("__ELF__");
464  if (Opts.POSIXThreads)
465  Builder.defineMacro("_REENTRANT");
466  }
467 public:
468  OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
469  this->UserLabelPrefix = "";
470  this->TLSSupported = false;
471 
472  switch (Triple.getArch()) {
473  default:
474  case llvm::Triple::x86:
475  case llvm::Triple::x86_64:
476  case llvm::Triple::arm:
477  case llvm::Triple::sparc:
478  this->MCountName = "__mcount";
479  break;
480  case llvm::Triple::mips64:
481  case llvm::Triple::mips64el:
482  case llvm::Triple::ppc:
483  case llvm::Triple::sparcv9:
484  this->MCountName = "_mcount";
485  break;
486  }
487  }
488 };
489 
490 // Bitrig Target
491 template<typename Target>
492 class BitrigTargetInfo : public OSTargetInfo<Target> {
493 protected:
494  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495  MacroBuilder &Builder) const override {
496  // Bitrig defines; list based off of gcc output
497 
498  Builder.defineMacro("__Bitrig__");
499  DefineStd(Builder, "unix", Opts);
500  Builder.defineMacro("__ELF__");
501  if (Opts.POSIXThreads)
502  Builder.defineMacro("_REENTRANT");
503 
504  switch (Triple.getArch()) {
505  default:
506  break;
507  case llvm::Triple::arm:
508  case llvm::Triple::armeb:
509  case llvm::Triple::thumb:
510  case llvm::Triple::thumbeb:
511  Builder.defineMacro("__ARM_DWARF_EH__");
512  break;
513  }
514  }
515 public:
516  BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
517  this->UserLabelPrefix = "";
518  this->MCountName = "__mcount";
519  }
520 };
521 
522 // PSP Target
523 template<typename Target>
524 class PSPTargetInfo : public OSTargetInfo<Target> {
525 protected:
526  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
527  MacroBuilder &Builder) const override {
528  // PSP defines; list based on the output of the pspdev gcc toolchain.
529  Builder.defineMacro("PSP");
530  Builder.defineMacro("_PSP");
531  Builder.defineMacro("__psp__");
532  Builder.defineMacro("__ELF__");
533  }
534 public:
535  PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
536  this->UserLabelPrefix = "";
537  }
538 };
539 
540 // PS3 PPU Target
541 template<typename Target>
542 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
543 protected:
544  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
545  MacroBuilder &Builder) const override {
546  // PS3 PPU defines.
547  Builder.defineMacro("__PPC__");
548  Builder.defineMacro("__PPU__");
549  Builder.defineMacro("__CELLOS_LV2__");
550  Builder.defineMacro("__ELF__");
551  Builder.defineMacro("__LP32__");
552  Builder.defineMacro("_ARCH_PPC64");
553  Builder.defineMacro("__powerpc64__");
554  }
555 public:
556  PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
557  this->UserLabelPrefix = "";
558  this->LongWidth = this->LongAlign = 32;
559  this->PointerWidth = this->PointerAlign = 32;
560  this->IntMaxType = TargetInfo::SignedLongLong;
561  this->Int64Type = TargetInfo::SignedLongLong;
562  this->SizeType = TargetInfo::UnsignedInt;
563  this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
564  }
565 };
566 
567 template <typename Target>
568 class PS4OSTargetInfo : public OSTargetInfo<Target> {
569 protected:
570  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
571  MacroBuilder &Builder) const override {
572  Builder.defineMacro("__FreeBSD__", "9");
573  Builder.defineMacro("__FreeBSD_cc_version", "900001");
574  Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
575  DefineStd(Builder, "unix", Opts);
576  Builder.defineMacro("__ELF__");
577  Builder.defineMacro("__PS4__");
578  }
579 public:
580  PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
581  this->WCharType = this->UnsignedShort;
582 
583  // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
584  this->MaxTLSAlign = 256;
585  this->UserLabelPrefix = "";
586 
587  switch (Triple.getArch()) {
588  default:
589  case llvm::Triple::x86_64:
590  this->MCountName = ".mcount";
591  break;
592  }
593  }
594 };
595 
596 // Solaris target
597 template<typename Target>
598 class SolarisTargetInfo : public OSTargetInfo<Target> {
599 protected:
600  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
601  MacroBuilder &Builder) const override {
602  DefineStd(Builder, "sun", Opts);
603  DefineStd(Builder, "unix", Opts);
604  Builder.defineMacro("__ELF__");
605  Builder.defineMacro("__svr4__");
606  Builder.defineMacro("__SVR4");
607  // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
608  // newer, but to 500 for everything else. feature_test.h has a check to
609  // ensure that you are not using C99 with an old version of X/Open or C89
610  // with a new version.
611  if (Opts.C99)
612  Builder.defineMacro("_XOPEN_SOURCE", "600");
613  else
614  Builder.defineMacro("_XOPEN_SOURCE", "500");
615  if (Opts.CPlusPlus)
616  Builder.defineMacro("__C99FEATURES__");
617  Builder.defineMacro("_LARGEFILE_SOURCE");
618  Builder.defineMacro("_LARGEFILE64_SOURCE");
619  Builder.defineMacro("__EXTENSIONS__");
620  Builder.defineMacro("_REENTRANT");
621  }
622 public:
623  SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
624  this->UserLabelPrefix = "";
625  this->WCharType = this->SignedInt;
626  // FIXME: WIntType should be SignedLong
627  }
628 };
629 
630 // Windows target
631 template<typename Target>
632 class WindowsTargetInfo : public OSTargetInfo<Target> {
633 protected:
634  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
635  MacroBuilder &Builder) const override {
636  Builder.defineMacro("_WIN32");
637  }
638  void getVisualStudioDefines(const LangOptions &Opts,
639  MacroBuilder &Builder) const {
640  if (Opts.CPlusPlus) {
641  if (Opts.RTTIData)
642  Builder.defineMacro("_CPPRTTI");
643 
644  if (Opts.CXXExceptions)
645  Builder.defineMacro("_CPPUNWIND");
646  }
647 
648  if (!Opts.CharIsSigned)
649  Builder.defineMacro("_CHAR_UNSIGNED");
650 
651  // FIXME: POSIXThreads isn't exactly the option this should be defined for,
652  // but it works for now.
653  if (Opts.POSIXThreads)
654  Builder.defineMacro("_MT");
655 
656  if (Opts.MSCompatibilityVersion) {
657  Builder.defineMacro("_MSC_VER",
658  Twine(Opts.MSCompatibilityVersion / 100000));
659  Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
660  // FIXME We cannot encode the revision information into 32-bits
661  Builder.defineMacro("_MSC_BUILD", Twine(1));
662 
663  if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
664  Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
665  }
666 
667  if (Opts.MicrosoftExt) {
668  Builder.defineMacro("_MSC_EXTENSIONS");
669 
670  if (Opts.CPlusPlus11) {
671  Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
672  Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
673  Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
674  }
675  }
676 
677  Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
678  }
679 
680 public:
681  WindowsTargetInfo(const llvm::Triple &Triple)
682  : OSTargetInfo<Target>(Triple) {}
683 };
684 
685 template <typename Target>
686 class NaClTargetInfo : public OSTargetInfo<Target> {
687 protected:
688  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
689  MacroBuilder &Builder) const override {
690  if (Opts.POSIXThreads)
691  Builder.defineMacro("_REENTRANT");
692  if (Opts.CPlusPlus)
693  Builder.defineMacro("_GNU_SOURCE");
694 
695  DefineStd(Builder, "unix", Opts);
696  Builder.defineMacro("__ELF__");
697  Builder.defineMacro("__native_client__");
698  }
699 
700 public:
701  NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
702  this->UserLabelPrefix = "";
703  this->LongAlign = 32;
704  this->LongWidth = 32;
705  this->PointerAlign = 32;
706  this->PointerWidth = 32;
707  this->IntMaxType = TargetInfo::SignedLongLong;
708  this->Int64Type = TargetInfo::SignedLongLong;
709  this->DoubleAlign = 64;
710  this->LongDoubleWidth = 64;
711  this->LongDoubleAlign = 64;
712  this->LongLongWidth = 64;
713  this->LongLongAlign = 64;
714  this->SizeType = TargetInfo::UnsignedInt;
715  this->PtrDiffType = TargetInfo::SignedInt;
716  this->IntPtrType = TargetInfo::SignedInt;
717  // RegParmMax is inherited from the underlying architecture
718  this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
719  if (Triple.getArch() == llvm::Triple::arm) {
720  // Handled in ARM's setABI().
721  } else if (Triple.getArch() == llvm::Triple::x86) {
722  this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
723  } else if (Triple.getArch() == llvm::Triple::x86_64) {
724  this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
725  } else if (Triple.getArch() == llvm::Triple::mipsel) {
726  // Handled on mips' setDescriptionString.
727  } else {
728  assert(Triple.getArch() == llvm::Triple::le32);
729  this->DescriptionString = "e-p:32:32-i64:64";
730  }
731  }
732 };
733 
734 //===----------------------------------------------------------------------===//
735 // Specific target implementations.
736 //===----------------------------------------------------------------------===//
737 
738 // PPC abstract base class
739 class PPCTargetInfo : public TargetInfo {
740  static const Builtin::Info BuiltinInfo[];
741  static const char * const GCCRegNames[];
742  static const TargetInfo::GCCRegAlias GCCRegAliases[];
743  std::string CPU;
744 
745  // Target cpu features.
746  bool HasVSX;
747  bool HasP8Vector;
748  bool HasP8Crypto;
749  bool HasDirectMove;
750  bool HasQPX;
751  bool HasHTM;
752  bool HasBPERMD;
753  bool HasExtDiv;
754 
755 protected:
756  std::string ABI;
757 
758 public:
759  PPCTargetInfo(const llvm::Triple &Triple)
760  : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
761  HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
762  HasBPERMD(false), HasExtDiv(false) {
763  BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
764  SimdDefaultAlign = 128;
765  LongDoubleWidth = LongDoubleAlign = 128;
766  LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
767  }
768 
769  /// \brief Flags for architecture specific defines.
770  typedef enum {
771  ArchDefineNone = 0,
772  ArchDefineName = 1 << 0, // <name> is substituted for arch name.
773  ArchDefinePpcgr = 1 << 1,
774  ArchDefinePpcsq = 1 << 2,
775  ArchDefine440 = 1 << 3,
776  ArchDefine603 = 1 << 4,
777  ArchDefine604 = 1 << 5,
778  ArchDefinePwr4 = 1 << 6,
779  ArchDefinePwr5 = 1 << 7,
780  ArchDefinePwr5x = 1 << 8,
781  ArchDefinePwr6 = 1 << 9,
782  ArchDefinePwr6x = 1 << 10,
783  ArchDefinePwr7 = 1 << 11,
784  ArchDefinePwr8 = 1 << 12,
785  ArchDefineA2 = 1 << 13,
786  ArchDefineA2q = 1 << 14
787  } ArchDefineTypes;
788 
789  // Note: GCC recognizes the following additional cpus:
790  // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
791  // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
792  // titan, rs64.
793  bool setCPU(const std::string &Name) override {
794  bool CPUKnown = llvm::StringSwitch<bool>(Name)
795  .Case("generic", true)
796  .Case("440", true)
797  .Case("450", true)
798  .Case("601", true)
799  .Case("602", true)
800  .Case("603", true)
801  .Case("603e", true)
802  .Case("603ev", true)
803  .Case("604", true)
804  .Case("604e", true)
805  .Case("620", true)
806  .Case("630", true)
807  .Case("g3", true)
808  .Case("7400", true)
809  .Case("g4", true)
810  .Case("7450", true)
811  .Case("g4+", true)
812  .Case("750", true)
813  .Case("970", true)
814  .Case("g5", true)
815  .Case("a2", true)
816  .Case("a2q", true)
817  .Case("e500mc", true)
818  .Case("e5500", true)
819  .Case("power3", true)
820  .Case("pwr3", true)
821  .Case("power4", true)
822  .Case("pwr4", true)
823  .Case("power5", true)
824  .Case("pwr5", true)
825  .Case("power5x", true)
826  .Case("pwr5x", true)
827  .Case("power6", true)
828  .Case("pwr6", true)
829  .Case("power6x", true)
830  .Case("pwr6x", true)
831  .Case("power7", true)
832  .Case("pwr7", true)
833  .Case("power8", true)
834  .Case("pwr8", true)
835  .Case("powerpc", true)
836  .Case("ppc", true)
837  .Case("powerpc64", true)
838  .Case("ppc64", true)
839  .Case("powerpc64le", true)
840  .Case("ppc64le", true)
841  .Default(false);
842 
843  if (CPUKnown)
844  CPU = Name;
845 
846  return CPUKnown;
847  }
848 
849 
850  StringRef getABI() const override { return ABI; }
851 
852  void getTargetBuiltins(const Builtin::Info *&Records,
853  unsigned &NumRecords) const override {
854  Records = BuiltinInfo;
856  }
857 
858  bool isCLZForZeroUndef() const override { return false; }
859 
860  void getTargetDefines(const LangOptions &Opts,
861  MacroBuilder &Builder) const override;
862 
863  void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
864 
865  bool handleTargetFeatures(std::vector<std::string> &Features,
866  DiagnosticsEngine &Diags) override;
867  bool hasFeature(StringRef Feature) const override;
868  void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
869  bool Enabled) const override;
870 
871  void getGCCRegNames(const char * const *&Names,
872  unsigned &NumNames) const override;
873  void getGCCRegAliases(const GCCRegAlias *&Aliases,
874  unsigned &NumAliases) const override;
875  bool validateAsmConstraint(const char *&Name,
876  TargetInfo::ConstraintInfo &Info) const override {
877  switch (*Name) {
878  default: return false;
879  case 'O': // Zero
880  break;
881  case 'b': // Base register
882  case 'f': // Floating point register
883  Info.setAllowsRegister();
884  break;
885  // FIXME: The following are added to allow parsing.
886  // I just took a guess at what the actions should be.
887  // Also, is more specific checking needed? I.e. specific registers?
888  case 'd': // Floating point register (containing 64-bit value)
889  case 'v': // Altivec vector register
890  Info.setAllowsRegister();
891  break;
892  case 'w':
893  switch (Name[1]) {
894  case 'd':// VSX vector register to hold vector double data
895  case 'f':// VSX vector register to hold vector float data
896  case 's':// VSX vector register to hold scalar float data
897  case 'a':// Any VSX register
898  case 'c':// An individual CR bit
899  break;
900  default:
901  return false;
902  }
903  Info.setAllowsRegister();
904  Name++; // Skip over 'w'.
905  break;
906  case 'h': // `MQ', `CTR', or `LINK' register
907  case 'q': // `MQ' register
908  case 'c': // `CTR' register
909  case 'l': // `LINK' register
910  case 'x': // `CR' register (condition register) number 0
911  case 'y': // `CR' register (condition register)
912  case 'z': // `XER[CA]' carry bit (part of the XER register)
913  Info.setAllowsRegister();
914  break;
915  case 'I': // Signed 16-bit constant
916  case 'J': // Unsigned 16-bit constant shifted left 16 bits
917  // (use `L' instead for SImode constants)
918  case 'K': // Unsigned 16-bit constant
919  case 'L': // Signed 16-bit constant shifted left 16 bits
920  case 'M': // Constant larger than 31
921  case 'N': // Exact power of 2
922  case 'P': // Constant whose negation is a signed 16-bit constant
923  case 'G': // Floating point constant that can be loaded into a
924  // register with one instruction per word
925  case 'H': // Integer/Floating point constant that can be loaded
926  // into a register using three instructions
927  break;
928  case 'm': // Memory operand. Note that on PowerPC targets, m can
929  // include addresses that update the base register. It
930  // is therefore only safe to use `m' in an asm statement
931  // if that asm statement accesses the operand exactly once.
932  // The asm statement must also use `%U<opno>' as a
933  // placeholder for the "update" flag in the corresponding
934  // load or store instruction. For example:
935  // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
936  // is correct but:
937  // asm ("st %1,%0" : "=m" (mem) : "r" (val));
938  // is not. Use es rather than m if you don't want the base
939  // register to be updated.
940  case 'e':
941  if (Name[1] != 's')
942  return false;
943  // es: A "stable" memory operand; that is, one which does not
944  // include any automodification of the base register. Unlike
945  // `m', this constraint can be used in asm statements that
946  // might access the operand several times, or that might not
947  // access it at all.
948  Info.setAllowsMemory();
949  Name++; // Skip over 'e'.
950  break;
951  case 'Q': // Memory operand that is an offset from a register (it is
952  // usually better to use `m' or `es' in asm statements)
953  case 'Z': // Memory operand that is an indexed or indirect from a
954  // register (it is usually better to use `m' or `es' in
955  // asm statements)
956  Info.setAllowsMemory();
957  Info.setAllowsRegister();
958  break;
959  case 'R': // AIX TOC entry
960  case 'a': // Address operand that is an indexed or indirect from a
961  // register (`p' is preferable for asm statements)
962  case 'S': // Constant suitable as a 64-bit mask operand
963  case 'T': // Constant suitable as a 32-bit mask operand
964  case 'U': // System V Release 4 small data area reference
965  case 't': // AND masks that can be performed by two rldic{l, r}
966  // instructions
967  case 'W': // Vector constant that does not require memory
968  case 'j': // Vector constant that is all zeros.
969  break;
970  // End FIXME.
971  }
972  return true;
973  }
974  std::string convertConstraint(const char *&Constraint) const override {
975  std::string R;
976  switch (*Constraint) {
977  case 'e':
978  case 'w':
979  // Two-character constraint; add "^" hint for later parsing.
980  R = std::string("^") + std::string(Constraint, 2);
981  Constraint++;
982  break;
983  default:
984  return TargetInfo::convertConstraint(Constraint);
985  }
986  return R;
987  }
988  const char *getClobbers() const override {
989  return "";
990  }
991  int getEHDataRegisterNumber(unsigned RegNo) const override {
992  if (RegNo == 0) return 3;
993  if (RegNo == 1) return 4;
994  return -1;
995  }
996 
997  bool hasSjLjLowering() const override {
998  return true;
999  }
1000 
1001  bool useFloat128ManglingForLongDouble() const override {
1002  return LongDoubleWidth == 128 &&
1003  LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble &&
1004  getTriple().isOSBinFormatELF();
1005  }
1006 };
1007 
1009 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1010 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1011  ALL_LANGUAGES },
1012 #include "clang/Basic/BuiltinsPPC.def"
1013 };
1014 
1015 /// handleTargetFeatures - Perform initialization based on the user
1016 /// configured set of features.
1017 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1018  DiagnosticsEngine &Diags) {
1019  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
1020  // Ignore disabled features.
1021  if (Features[i][0] == '-')
1022  continue;
1023 
1024  StringRef Feature = StringRef(Features[i]).substr(1);
1025 
1026  if (Feature == "vsx") {
1027  HasVSX = true;
1028  continue;
1029  }
1030 
1031  if (Feature == "bpermd") {
1032  HasBPERMD = true;
1033  continue;
1034  }
1035 
1036  if (Feature == "extdiv") {
1037  HasExtDiv = true;
1038  continue;
1039  }
1040 
1041  if (Feature == "power8-vector") {
1042  HasP8Vector = true;
1043  continue;
1044  }
1045 
1046  if (Feature == "crypto") {
1047  HasP8Crypto = true;
1048  continue;
1049  }
1050 
1051  if (Feature == "direct-move") {
1052  HasDirectMove = true;
1053  continue;
1054  }
1055 
1056  if (Feature == "qpx") {
1057  HasQPX = true;
1058  continue;
1059  }
1060 
1061  if (Feature == "htm") {
1062  HasHTM = true;
1063  continue;
1064  }
1065 
1066  // TODO: Finish this list and add an assert that we've handled them
1067  // all.
1068  }
1069  if (!HasVSX && (HasP8Vector || HasDirectMove)) {
1070  if (HasP8Vector)
1071  Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" <<
1072  "-mno-vsx";
1073  else if (HasDirectMove)
1074  Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" <<
1075  "-mno-vsx";
1076  return false;
1077  }
1078 
1079  return true;
1080 }
1081 
1082 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1083 /// #defines that are not tied to a specific subtarget.
1084 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1085  MacroBuilder &Builder) const {
1086  // Target identification.
1087  Builder.defineMacro("__ppc__");
1088  Builder.defineMacro("__PPC__");
1089  Builder.defineMacro("_ARCH_PPC");
1090  Builder.defineMacro("__powerpc__");
1091  Builder.defineMacro("__POWERPC__");
1092  if (PointerWidth == 64) {
1093  Builder.defineMacro("_ARCH_PPC64");
1094  Builder.defineMacro("__powerpc64__");
1095  Builder.defineMacro("__ppc64__");
1096  Builder.defineMacro("__PPC64__");
1097  }
1098 
1099  // Target properties.
1100  if (getTriple().getArch() == llvm::Triple::ppc64le) {
1101  Builder.defineMacro("_LITTLE_ENDIAN");
1102  } else {
1103  if (getTriple().getOS() != llvm::Triple::NetBSD &&
1104  getTriple().getOS() != llvm::Triple::OpenBSD)
1105  Builder.defineMacro("_BIG_ENDIAN");
1106  }
1107 
1108  // ABI options.
1109  if (ABI == "elfv1" || ABI == "elfv1-qpx")
1110  Builder.defineMacro("_CALL_ELF", "1");
1111  if (ABI == "elfv2")
1112  Builder.defineMacro("_CALL_ELF", "2");
1113 
1114  // Subtarget options.
1115  Builder.defineMacro("__NATURAL_ALIGNMENT__");
1116  Builder.defineMacro("__REGISTER_PREFIX__", "");
1117 
1118  // FIXME: Should be controlled by command line option.
1119  if (LongDoubleWidth == 128)
1120  Builder.defineMacro("__LONG_DOUBLE_128__");
1121 
1122  if (Opts.AltiVec) {
1123  Builder.defineMacro("__VEC__", "10206");
1124  Builder.defineMacro("__ALTIVEC__");
1125  }
1126 
1127  // CPU identification.
1128  ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1129  .Case("440", ArchDefineName)
1130  .Case("450", ArchDefineName | ArchDefine440)
1131  .Case("601", ArchDefineName)
1132  .Case("602", ArchDefineName | ArchDefinePpcgr)
1133  .Case("603", ArchDefineName | ArchDefinePpcgr)
1134  .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1135  .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1136  .Case("604", ArchDefineName | ArchDefinePpcgr)
1137  .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1138  .Case("620", ArchDefineName | ArchDefinePpcgr)
1139  .Case("630", ArchDefineName | ArchDefinePpcgr)
1140  .Case("7400", ArchDefineName | ArchDefinePpcgr)
1141  .Case("7450", ArchDefineName | ArchDefinePpcgr)
1142  .Case("750", ArchDefineName | ArchDefinePpcgr)
1143  .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1144  | ArchDefinePpcsq)
1145  .Case("a2", ArchDefineA2)
1146  .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1147  .Case("pwr3", ArchDefinePpcgr)
1148  .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1149  .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1150  | ArchDefinePpcsq)
1151  .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1152  | ArchDefinePpcgr | ArchDefinePpcsq)
1153  .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1154  | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1155  .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1156  | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1157  | ArchDefinePpcsq)
1158  .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1159  | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1160  | ArchDefinePpcgr | ArchDefinePpcsq)
1161  .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1162  | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1163  | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1164  .Case("power3", ArchDefinePpcgr)
1165  .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1166  .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1167  | ArchDefinePpcsq)
1168  .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1169  | ArchDefinePpcgr | ArchDefinePpcsq)
1170  .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1171  | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1172  .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1173  | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1174  | ArchDefinePpcsq)
1175  .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1176  | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1177  | ArchDefinePpcgr | ArchDefinePpcsq)
1178  .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1179  | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1180  | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1181  .Default(ArchDefineNone);
1182 
1183  if (defs & ArchDefineName)
1184  Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1185  if (defs & ArchDefinePpcgr)
1186  Builder.defineMacro("_ARCH_PPCGR");
1187  if (defs & ArchDefinePpcsq)
1188  Builder.defineMacro("_ARCH_PPCSQ");
1189  if (defs & ArchDefine440)
1190  Builder.defineMacro("_ARCH_440");
1191  if (defs & ArchDefine603)
1192  Builder.defineMacro("_ARCH_603");
1193  if (defs & ArchDefine604)
1194  Builder.defineMacro("_ARCH_604");
1195  if (defs & ArchDefinePwr4)
1196  Builder.defineMacro("_ARCH_PWR4");
1197  if (defs & ArchDefinePwr5)
1198  Builder.defineMacro("_ARCH_PWR5");
1199  if (defs & ArchDefinePwr5x)
1200  Builder.defineMacro("_ARCH_PWR5X");
1201  if (defs & ArchDefinePwr6)
1202  Builder.defineMacro("_ARCH_PWR6");
1203  if (defs & ArchDefinePwr6x)
1204  Builder.defineMacro("_ARCH_PWR6X");
1205  if (defs & ArchDefinePwr7)
1206  Builder.defineMacro("_ARCH_PWR7");
1207  if (defs & ArchDefinePwr8)
1208  Builder.defineMacro("_ARCH_PWR8");
1209  if (defs & ArchDefineA2)
1210  Builder.defineMacro("_ARCH_A2");
1211  if (defs & ArchDefineA2q) {
1212  Builder.defineMacro("_ARCH_A2Q");
1213  Builder.defineMacro("_ARCH_QP");
1214  }
1215 
1216  if (getTriple().getVendor() == llvm::Triple::BGQ) {
1217  Builder.defineMacro("__bg__");
1218  Builder.defineMacro("__THW_BLUEGENE__");
1219  Builder.defineMacro("__bgq__");
1220  Builder.defineMacro("__TOS_BGQ__");
1221  }
1222 
1223  if (HasVSX)
1224  Builder.defineMacro("__VSX__");
1225  if (HasP8Vector)
1226  Builder.defineMacro("__POWER8_VECTOR__");
1227  if (HasP8Crypto)
1228  Builder.defineMacro("__CRYPTO__");
1229  if (HasHTM)
1230  Builder.defineMacro("__HTM__");
1231  if (getTriple().getArch() == llvm::Triple::ppc64le ||
1232  (defs & ArchDefinePwr8) || (CPU == "pwr8")) {
1233  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1234  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1235  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1236  if (PointerWidth == 64)
1237  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1238  }
1239 
1240  // FIXME: The following are not yet generated here by Clang, but are
1241  // generated by GCC:
1242  //
1243  // _SOFT_FLOAT_
1244  // __RECIP_PRECISION__
1245  // __APPLE_ALTIVEC__
1246  // __RECIP__
1247  // __RECIPF__
1248  // __RSQRTE__
1249  // __RSQRTEF__
1250  // _SOFT_DOUBLE_
1251  // __NO_LWSYNC__
1252  // __HAVE_BSWAP__
1253  // __LONGDOUBLE128
1254  // __CMODEL_MEDIUM__
1255  // __CMODEL_LARGE__
1256  // _CALL_SYSV
1257  // _CALL_DARWIN
1258  // __NO_FPRS__
1259 }
1260 
1261 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1262  Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1263  .Case("7400", true)
1264  .Case("g4", true)
1265  .Case("7450", true)
1266  .Case("g4+", true)
1267  .Case("970", true)
1268  .Case("g5", true)
1269  .Case("pwr6", true)
1270  .Case("pwr7", true)
1271  .Case("pwr8", true)
1272  .Case("ppc64", true)
1273  .Case("ppc64le", true)
1274  .Default(false);
1275 
1276  Features["qpx"] = (CPU == "a2q");
1277  Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1278  .Case("ppc64le", true)
1279  .Case("pwr8", true)
1280  .Default(false);
1281  Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1282  .Case("ppc64le", true)
1283  .Case("pwr8", true)
1284  .Default(false);
1285  Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1286  .Case("ppc64le", true)
1287  .Case("pwr8", true)
1288  .Case("pwr7", true)
1289  .Default(false);
1290  Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1291  .Case("ppc64le", true)
1292  .Case("pwr8", true)
1293  .Case("pwr7", true)
1294  .Default(false);
1295  Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1296  .Case("ppc64le", true)
1297  .Case("pwr8", true)
1298  .Default(false);
1299  Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1300  .Case("ppc64le", true)
1301  .Case("pwr8", true)
1302  .Case("pwr7", true)
1303  .Default(false);
1304 }
1305 
1306 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1307  return llvm::StringSwitch<bool>(Feature)
1308  .Case("powerpc", true)
1309  .Case("vsx", HasVSX)
1310  .Case("power8-vector", HasP8Vector)
1311  .Case("crypto", HasP8Crypto)
1312  .Case("direct-move", HasDirectMove)
1313  .Case("qpx", HasQPX)
1314  .Case("htm", HasHTM)
1315  .Case("bpermd", HasBPERMD)
1316  .Case("extdiv", HasExtDiv)
1317  .Default(false);
1318 }
1319 
1320 /* There is no clear way for the target to know which of the features in the
1321  final feature vector came from defaults and which are actually specified by
1322  the user. To that end, we use the fact that this function is not called on
1323  default features - only user specified ones. By the first time this
1324  function is called, the default features are populated.
1325  We then keep track of the features that the user specified so that we
1326  can ensure we do not override a user's request (only defaults).
1327  For example:
1328  -mcpu=pwr8 -mno-vsx (should disable vsx and everything that depends on it)
1329  -mcpu=pwr8 -mdirect-move -mno-vsx (should actually be diagnosed)
1330 
1331 NOTE: Do not call this from PPCTargetInfo::getDefaultFeatures
1332 */
1333 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1334  StringRef Name, bool Enabled) const {
1335  static llvm::StringMap<bool> ExplicitFeatures;
1336  ExplicitFeatures[Name] = Enabled;
1337 
1338  // At this point, -mno-vsx turns off the dependent features but we respect
1339  // the user's requests.
1340  if (!Enabled && Name == "vsx") {
1341  Features["direct-move"] = ExplicitFeatures["direct-move"];
1342  Features["power8-vector"] = ExplicitFeatures["power8-vector"];
1343  }
1344  if ((Enabled && Name == "power8-vector") ||
1345  (Enabled && Name == "direct-move")) {
1346  if (ExplicitFeatures.find("vsx") == ExplicitFeatures.end()) {
1347  Features["vsx"] = true;
1348  }
1349  }
1350  Features[Name] = Enabled;
1351 }
1352 
1353 const char * const PPCTargetInfo::GCCRegNames[] = {
1354  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1355  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1356  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1357  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1358  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1359  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1360  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1361  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1362  "mq", "lr", "ctr", "ap",
1363  "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1364  "xer",
1365  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1366  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1367  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1368  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1369  "vrsave", "vscr",
1370  "spe_acc", "spefscr",
1371  "sfp"
1372 };
1373 
1374 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1375  unsigned &NumNames) const {
1376  Names = GCCRegNames;
1377  NumNames = llvm::array_lengthof(GCCRegNames);
1378 }
1379 
1380 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1381  // While some of these aliases do map to different registers
1382  // they still share the same register name.
1383  { { "0" }, "r0" },
1384  { { "1"}, "r1" },
1385  { { "2" }, "r2" },
1386  { { "3" }, "r3" },
1387  { { "4" }, "r4" },
1388  { { "5" }, "r5" },
1389  { { "6" }, "r6" },
1390  { { "7" }, "r7" },
1391  { { "8" }, "r8" },
1392  { { "9" }, "r9" },
1393  { { "10" }, "r10" },
1394  { { "11" }, "r11" },
1395  { { "12" }, "r12" },
1396  { { "13" }, "r13" },
1397  { { "14" }, "r14" },
1398  { { "15" }, "r15" },
1399  { { "16" }, "r16" },
1400  { { "17" }, "r17" },
1401  { { "18" }, "r18" },
1402  { { "19" }, "r19" },
1403  { { "20" }, "r20" },
1404  { { "21" }, "r21" },
1405  { { "22" }, "r22" },
1406  { { "23" }, "r23" },
1407  { { "24" }, "r24" },
1408  { { "25" }, "r25" },
1409  { { "26" }, "r26" },
1410  { { "27" }, "r27" },
1411  { { "28" }, "r28" },
1412  { { "29" }, "r29" },
1413  { { "30" }, "r30" },
1414  { { "31" }, "r31" },
1415  { { "fr0" }, "f0" },
1416  { { "fr1" }, "f1" },
1417  { { "fr2" }, "f2" },
1418  { { "fr3" }, "f3" },
1419  { { "fr4" }, "f4" },
1420  { { "fr5" }, "f5" },
1421  { { "fr6" }, "f6" },
1422  { { "fr7" }, "f7" },
1423  { { "fr8" }, "f8" },
1424  { { "fr9" }, "f9" },
1425  { { "fr10" }, "f10" },
1426  { { "fr11" }, "f11" },
1427  { { "fr12" }, "f12" },
1428  { { "fr13" }, "f13" },
1429  { { "fr14" }, "f14" },
1430  { { "fr15" }, "f15" },
1431  { { "fr16" }, "f16" },
1432  { { "fr17" }, "f17" },
1433  { { "fr18" }, "f18" },
1434  { { "fr19" }, "f19" },
1435  { { "fr20" }, "f20" },
1436  { { "fr21" }, "f21" },
1437  { { "fr22" }, "f22" },
1438  { { "fr23" }, "f23" },
1439  { { "fr24" }, "f24" },
1440  { { "fr25" }, "f25" },
1441  { { "fr26" }, "f26" },
1442  { { "fr27" }, "f27" },
1443  { { "fr28" }, "f28" },
1444  { { "fr29" }, "f29" },
1445  { { "fr30" }, "f30" },
1446  { { "fr31" }, "f31" },
1447  { { "cc" }, "cr0" },
1448 };
1449 
1450 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1451  unsigned &NumAliases) const {
1452  Aliases = GCCRegAliases;
1453  NumAliases = llvm::array_lengthof(GCCRegAliases);
1454 }
1455 
1456 class PPC32TargetInfo : public PPCTargetInfo {
1457 public:
1458  PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1459  DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1460 
1461  switch (getTriple().getOS()) {
1462  case llvm::Triple::Linux:
1463  case llvm::Triple::FreeBSD:
1464  case llvm::Triple::NetBSD:
1465  SizeType = UnsignedInt;
1466  PtrDiffType = SignedInt;
1467  IntPtrType = SignedInt;
1468  break;
1469  default:
1470  break;
1471  }
1472 
1473  if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1474  LongDoubleWidth = LongDoubleAlign = 64;
1475  LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1476  }
1477 
1478  // PPC32 supports atomics up to 4 bytes.
1479  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1480  }
1481 
1482  BuiltinVaListKind getBuiltinVaListKind() const override {
1483  // This is the ELF definition, and is overridden by the Darwin sub-target
1485  }
1486 };
1487 
1488 // Note: ABI differences may eventually require us to have a separate
1489 // TargetInfo for little endian.
1490 class PPC64TargetInfo : public PPCTargetInfo {
1491 public:
1492  PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1493  LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1494  IntMaxType = SignedLong;
1495  Int64Type = SignedLong;
1496 
1497  if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1498  DescriptionString = "e-m:e-i64:64-n32:64";
1499  ABI = "elfv2";
1500  } else {
1501  DescriptionString = "E-m:e-i64:64-n32:64";
1502  ABI = "elfv1";
1503  }
1504 
1505  switch (getTriple().getOS()) {
1506  case llvm::Triple::FreeBSD:
1507  LongDoubleWidth = LongDoubleAlign = 64;
1508  LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1509  break;
1510  case llvm::Triple::NetBSD:
1511  IntMaxType = SignedLongLong;
1512  Int64Type = SignedLongLong;
1513  break;
1514  default:
1515  break;
1516  }
1517 
1518  // PPC64 supports atomics up to 8 bytes.
1519  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1520  }
1521  BuiltinVaListKind getBuiltinVaListKind() const override {
1523  }
1524  // PPC64 Linux-specific ABI options.
1525  bool setABI(const std::string &Name) override {
1526  if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1527  ABI = Name;
1528  return true;
1529  }
1530  return false;
1531  }
1532 };
1533 
1534 class DarwinPPC32TargetInfo :
1535  public DarwinTargetInfo<PPC32TargetInfo> {
1536 public:
1537  DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1538  : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1539  HasAlignMac68kSupport = true;
1540  BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1541  PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1542  LongLongAlign = 32;
1543  SuitableAlign = 128;
1544  DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1545  }
1546  BuiltinVaListKind getBuiltinVaListKind() const override {
1548  }
1549 };
1550 
1551 class DarwinPPC64TargetInfo :
1552  public DarwinTargetInfo<PPC64TargetInfo> {
1553 public:
1554  DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1555  : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1556  HasAlignMac68kSupport = true;
1557  SuitableAlign = 128;
1558  DescriptionString = "E-m:o-i64:64-n32:64";
1559  }
1560 };
1561 
1562  static const unsigned NVPTXAddrSpaceMap[] = {
1563  1, // opencl_global
1564  3, // opencl_local
1565  4, // opencl_constant
1566  // FIXME: generic has to be added to the target
1567  0, // opencl_generic
1568  1, // cuda_device
1569  4, // cuda_constant
1570  3, // cuda_shared
1571  };
1572  class NVPTXTargetInfo : public TargetInfo {
1573  static const char * const GCCRegNames[];
1574  static const Builtin::Info BuiltinInfo[];
1575 
1576  // The GPU profiles supported by the NVPTX backend
1577  enum GPUKind {
1578  GK_NONE,
1579  GK_SM20,
1580  GK_SM21,
1581  GK_SM30,
1582  GK_SM35,
1583  GK_SM37,
1584  } GPU;
1585 
1586  public:
1587  NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1588  BigEndian = false;
1589  TLSSupported = false;
1590  LongWidth = LongAlign = 64;
1591  AddrSpaceMap = &NVPTXAddrSpaceMap;
1592  UseAddrSpaceMapMangling = true;
1593  // Define available target features
1594  // These must be defined in sorted order!
1595  NoAsmVariants = true;
1596  // Set the default GPU to sm20
1597  GPU = GK_SM20;
1598  }
1599  void getTargetDefines(const LangOptions &Opts,
1600  MacroBuilder &Builder) const override {
1601  Builder.defineMacro("__PTX__");
1602  Builder.defineMacro("__NVPTX__");
1603  if (Opts.CUDAIsDevice) {
1604  // Set __CUDA_ARCH__ for the GPU specified.
1605  std::string CUDAArchCode;
1606  switch (GPU) {
1607  case GK_SM20:
1608  CUDAArchCode = "200";
1609  break;
1610  case GK_SM21:
1611  CUDAArchCode = "210";
1612  break;
1613  case GK_SM30:
1614  CUDAArchCode = "300";
1615  break;
1616  case GK_SM35:
1617  CUDAArchCode = "350";
1618  break;
1619  case GK_SM37:
1620  CUDAArchCode = "370";
1621  break;
1622  default:
1623  llvm_unreachable("Unhandled target CPU");
1624  }
1625  Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1626  }
1627  }
1628  void getTargetBuiltins(const Builtin::Info *&Records,
1629  unsigned &NumRecords) const override {
1630  Records = BuiltinInfo;
1632  }
1633  bool hasFeature(StringRef Feature) const override {
1634  return Feature == "ptx" || Feature == "nvptx";
1635  }
1636 
1637  void getGCCRegNames(const char * const *&Names,
1638  unsigned &NumNames) const override;
1639  void getGCCRegAliases(const GCCRegAlias *&Aliases,
1640  unsigned &NumAliases) const override {
1641  // No aliases.
1642  Aliases = nullptr;
1643  NumAliases = 0;
1644  }
1645  bool
1646  validateAsmConstraint(const char *&Name,
1647  TargetInfo::ConstraintInfo &Info) const override {
1648  switch (*Name) {
1649  default: return false;
1650  case 'c':
1651  case 'h':
1652  case 'r':
1653  case 'l':
1654  case 'f':
1655  case 'd':
1656  Info.setAllowsRegister();
1657  return true;
1658  }
1659  }
1660  const char *getClobbers() const override {
1661  // FIXME: Is this really right?
1662  return "";
1663  }
1664  BuiltinVaListKind getBuiltinVaListKind() const override {
1665  // FIXME: implement
1667  }
1668  bool setCPU(const std::string &Name) override {
1669  GPU = llvm::StringSwitch<GPUKind>(Name)
1670  .Case("sm_20", GK_SM20)
1671  .Case("sm_21", GK_SM21)
1672  .Case("sm_30", GK_SM30)
1673  .Case("sm_35", GK_SM35)
1674  .Case("sm_37", GK_SM37)
1675  .Default(GK_NONE);
1676 
1677  return GPU != GK_NONE;
1678  }
1679  };
1680 
1682 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1683 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1684  ALL_LANGUAGES },
1685 #include "clang/Basic/BuiltinsNVPTX.def"
1686  };
1687 
1688  const char * const NVPTXTargetInfo::GCCRegNames[] = {
1689  "r0"
1690  };
1691 
1692  void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1693  unsigned &NumNames) const {
1694  Names = GCCRegNames;
1695  NumNames = llvm::array_lengthof(GCCRegNames);
1696  }
1697 
1698  class NVPTX32TargetInfo : public NVPTXTargetInfo {
1699  public:
1700  NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1701  PointerWidth = PointerAlign = 32;
1702  SizeType = TargetInfo::UnsignedInt;
1703  PtrDiffType = TargetInfo::SignedInt;
1704  IntPtrType = TargetInfo::SignedInt;
1705  DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1706  }
1707  };
1708 
1709  class NVPTX64TargetInfo : public NVPTXTargetInfo {
1710  public:
1711  NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1712  PointerWidth = PointerAlign = 64;
1713  SizeType = TargetInfo::UnsignedLong;
1714  PtrDiffType = TargetInfo::SignedLong;
1715  IntPtrType = TargetInfo::SignedLong;
1716  DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1717  }
1718  };
1719 
1720 static const unsigned AMDGPUAddrSpaceMap[] = {
1721  1, // opencl_global
1722  3, // opencl_local
1723  2, // opencl_constant
1724  4, // opencl_generic
1725  1, // cuda_device
1726  2, // cuda_constant
1727  3 // cuda_shared
1728 };
1729 
1730 // If you edit the description strings, make sure you update
1731 // getPointerWidthV().
1732 
1733 static const char *DescriptionStringR600 =
1734  "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1735  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1736 
1737 static const char *DescriptionStringR600DoubleOps =
1738  "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1739  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1740 
1741 static const char *DescriptionStringSI =
1742  "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1743  "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1744  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1745 
1746 class AMDGPUTargetInfo : public TargetInfo {
1747  static const Builtin::Info BuiltinInfo[];
1748  static const char * const GCCRegNames[];
1749 
1750  /// \brief The GPU profiles supported by the AMDGPU target.
1751  enum GPUKind {
1752  GK_NONE,
1753  GK_R600,
1754  GK_R600_DOUBLE_OPS,
1755  GK_R700,
1756  GK_R700_DOUBLE_OPS,
1757  GK_EVERGREEN,
1758  GK_EVERGREEN_DOUBLE_OPS,
1759  GK_NORTHERN_ISLANDS,
1760  GK_CAYMAN,
1761  GK_SOUTHERN_ISLANDS,
1762  GK_SEA_ISLANDS,
1763  GK_VOLCANIC_ISLANDS
1764  } GPU;
1765 
1766  bool hasFP64:1;
1767  bool hasFMAF:1;
1768  bool hasLDEXPF:1;
1769 
1770 public:
1771  AMDGPUTargetInfo(const llvm::Triple &Triple)
1772  : TargetInfo(Triple) {
1773 
1774  if (Triple.getArch() == llvm::Triple::amdgcn) {
1775  DescriptionString = DescriptionStringSI;
1776  GPU = GK_SOUTHERN_ISLANDS;
1777  hasFP64 = true;
1778  hasFMAF = true;
1779  hasLDEXPF = true;
1780  } else {
1781  DescriptionString = DescriptionStringR600;
1782  GPU = GK_R600;
1783  hasFP64 = false;
1784  hasFMAF = false;
1785  hasLDEXPF = false;
1786  }
1787  AddrSpaceMap = &AMDGPUAddrSpaceMap;
1788  UseAddrSpaceMapMangling = true;
1789  }
1790 
1791  uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1792  if (GPU <= GK_CAYMAN)
1793  return 32;
1794 
1795  switch(AddrSpace) {
1796  default:
1797  return 64;
1798  case 0:
1799  case 3:
1800  case 5:
1801  return 32;
1802  }
1803  }
1804 
1805  const char * getClobbers() const override {
1806  return "";
1807  }
1808 
1809  void getGCCRegNames(const char * const *&Names,
1810  unsigned &NumNames) const override;
1811 
1812  void getGCCRegAliases(const GCCRegAlias *&Aliases,
1813  unsigned &NumAliases) const override {
1814  Aliases = nullptr;
1815  NumAliases = 0;
1816  }
1817 
1818  bool validateAsmConstraint(const char *&Name,
1819  TargetInfo::ConstraintInfo &info) const override {
1820  return true;
1821  }
1822 
1823  void getTargetBuiltins(const Builtin::Info *&Records,
1824  unsigned &NumRecords) const override {
1825  Records = BuiltinInfo;
1827  }
1828 
1829  void getTargetDefines(const LangOptions &Opts,
1830  MacroBuilder &Builder) const override {
1831  Builder.defineMacro("__R600__");
1832  if (hasFMAF)
1833  Builder.defineMacro("__HAS_FMAF__");
1834  if (hasLDEXPF)
1835  Builder.defineMacro("__HAS_LDEXPF__");
1836  if (hasFP64 && Opts.OpenCL) {
1837  Builder.defineMacro("cl_khr_fp64");
1838  }
1839  }
1840 
1841  BuiltinVaListKind getBuiltinVaListKind() const override {
1843  }
1844 
1845  bool setCPU(const std::string &Name) override {
1846  GPU = llvm::StringSwitch<GPUKind>(Name)
1847  .Case("r600" , GK_R600)
1848  .Case("rv610", GK_R600)
1849  .Case("rv620", GK_R600)
1850  .Case("rv630", GK_R600)
1851  .Case("rv635", GK_R600)
1852  .Case("rs780", GK_R600)
1853  .Case("rs880", GK_R600)
1854  .Case("rv670", GK_R600_DOUBLE_OPS)
1855  .Case("rv710", GK_R700)
1856  .Case("rv730", GK_R700)
1857  .Case("rv740", GK_R700_DOUBLE_OPS)
1858  .Case("rv770", GK_R700_DOUBLE_OPS)
1859  .Case("palm", GK_EVERGREEN)
1860  .Case("cedar", GK_EVERGREEN)
1861  .Case("sumo", GK_EVERGREEN)
1862  .Case("sumo2", GK_EVERGREEN)
1863  .Case("redwood", GK_EVERGREEN)
1864  .Case("juniper", GK_EVERGREEN)
1865  .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1866  .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1867  .Case("barts", GK_NORTHERN_ISLANDS)
1868  .Case("turks", GK_NORTHERN_ISLANDS)
1869  .Case("caicos", GK_NORTHERN_ISLANDS)
1870  .Case("cayman", GK_CAYMAN)
1871  .Case("aruba", GK_CAYMAN)
1872  .Case("tahiti", GK_SOUTHERN_ISLANDS)
1873  .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1874  .Case("verde", GK_SOUTHERN_ISLANDS)
1875  .Case("oland", GK_SOUTHERN_ISLANDS)
1876  .Case("hainan", GK_SOUTHERN_ISLANDS)
1877  .Case("bonaire", GK_SEA_ISLANDS)
1878  .Case("kabini", GK_SEA_ISLANDS)
1879  .Case("kaveri", GK_SEA_ISLANDS)
1880  .Case("hawaii", GK_SEA_ISLANDS)
1881  .Case("mullins", GK_SEA_ISLANDS)
1882  .Case("tonga", GK_VOLCANIC_ISLANDS)
1883  .Case("iceland", GK_VOLCANIC_ISLANDS)
1884  .Case("carrizo", GK_VOLCANIC_ISLANDS)
1885  .Default(GK_NONE);
1886 
1887  if (GPU == GK_NONE) {
1888  return false;
1889  }
1890 
1891  // Set the correct data layout
1892  switch (GPU) {
1893  case GK_NONE:
1894  case GK_R600:
1895  case GK_R700:
1896  case GK_EVERGREEN:
1897  case GK_NORTHERN_ISLANDS:
1898  DescriptionString = DescriptionStringR600;
1899  hasFP64 = false;
1900  hasFMAF = false;
1901  hasLDEXPF = false;
1902  break;
1903  case GK_R600_DOUBLE_OPS:
1904  case GK_R700_DOUBLE_OPS:
1905  case GK_EVERGREEN_DOUBLE_OPS:
1906  case GK_CAYMAN:
1907  DescriptionString = DescriptionStringR600DoubleOps;
1908  hasFP64 = true;
1909  hasFMAF = true;
1910  hasLDEXPF = false;
1911  break;
1912  case GK_SOUTHERN_ISLANDS:
1913  case GK_SEA_ISLANDS:
1914  case GK_VOLCANIC_ISLANDS:
1915  DescriptionString = DescriptionStringSI;
1916  hasFP64 = true;
1917  hasFMAF = true;
1918  hasLDEXPF = true;
1919  break;
1920  }
1921 
1922  return true;
1923  }
1924 };
1925 
1927 #define BUILTIN(ID, TYPE, ATTRS) \
1928  { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1929 #include "clang/Basic/BuiltinsAMDGPU.def"
1930 };
1931 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
1932  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1933  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1934  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1935  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1936  "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
1937  "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
1938  "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
1939  "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
1940  "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
1941  "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
1942  "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
1943  "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
1944  "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
1945  "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
1946  "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
1947  "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
1948  "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
1949  "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
1950  "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
1951  "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
1952  "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
1953  "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
1954  "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
1955  "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
1956  "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
1957  "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
1958  "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
1959  "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
1960  "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
1961  "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
1962  "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
1963  "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
1964  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1965  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
1966  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
1967  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1968  "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
1969  "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
1970  "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
1971  "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
1972  "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
1973  "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
1974  "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
1975  "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
1976  "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
1977  "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
1978  "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
1979  "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127"
1980  "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi",
1981  "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi"
1982 };
1983 
1984 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names,
1985  unsigned &NumNames) const {
1986  Names = GCCRegNames;
1987  NumNames = llvm::array_lengthof(GCCRegNames);
1988 }
1989 
1990 // Namespace for x86 abstract base class
1991 const Builtin::Info BuiltinInfo[] = {
1992 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1993 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1994  ALL_LANGUAGES },
1995 #include "clang/Basic/BuiltinsX86.def"
1996 };
1997 
1998 static const char* const GCCRegNames[] = {
1999  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2000  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2001  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2002  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2003  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2004  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2005  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2006  "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2007  "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2008 };
2009 
2010 const TargetInfo::AddlRegName AddlRegNames[] = {
2011  { { "al", "ah", "eax", "rax" }, 0 },
2012  { { "bl", "bh", "ebx", "rbx" }, 3 },
2013  { { "cl", "ch", "ecx", "rcx" }, 2 },
2014  { { "dl", "dh", "edx", "rdx" }, 1 },
2015  { { "esi", "rsi" }, 4 },
2016  { { "edi", "rdi" }, 5 },
2017  { { "esp", "rsp" }, 7 },
2018  { { "ebp", "rbp" }, 6 },
2019 };
2020 
2021 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2022 // most of the implementation can be shared.
2023 class X86TargetInfo : public TargetInfo {
2024  enum X86SSEEnum {
2025  NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2026  } SSELevel;
2027  enum MMX3DNowEnum {
2028  NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2029  } MMX3DNowLevel;
2030  enum XOPEnum {
2031  NoXOP,
2032  SSE4A,
2033  FMA4,
2034  XOP
2035  } XOPLevel;
2036 
2037  bool HasAES;
2038  bool HasPCLMUL;
2039  bool HasLZCNT;
2040  bool HasRDRND;
2041  bool HasFSGSBASE;
2042  bool HasBMI;
2043  bool HasBMI2;
2044  bool HasPOPCNT;
2045  bool HasRTM;
2046  bool HasPRFCHW;
2047  bool HasRDSEED;
2048  bool HasADX;
2049  bool HasTBM;
2050  bool HasFMA;
2051  bool HasF16C;
2052  bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
2053  HasAVX512VL;
2054  bool HasSHA;
2055  bool HasCX16;
2056 
2057  /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2058  ///
2059  /// Each enumeration represents a particular CPU supported by Clang. These
2060  /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2061  enum CPUKind {
2062  CK_Generic,
2063 
2064  /// \name i386
2065  /// i386-generation processors.
2066  //@{
2067  CK_i386,
2068  //@}
2069 
2070  /// \name i486
2071  /// i486-generation processors.
2072  //@{
2073  CK_i486,
2074  CK_WinChipC6,
2075  CK_WinChip2,
2076  CK_C3,
2077  //@}
2078 
2079  /// \name i586
2080  /// i586-generation processors, P5 microarchitecture based.
2081  //@{
2082  CK_i586,
2083  CK_Pentium,
2084  CK_PentiumMMX,
2085  //@}
2086 
2087  /// \name i686
2088  /// i686-generation processors, P6 / Pentium M microarchitecture based.
2089  //@{
2090  CK_i686,
2091  CK_PentiumPro,
2092  CK_Pentium2,
2093  CK_Pentium3,
2094  CK_Pentium3M,
2095  CK_PentiumM,
2096  CK_C3_2,
2097 
2098  /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2099  /// Clang however has some logic to suport this.
2100  // FIXME: Warn, deprecate, and potentially remove this.
2101  CK_Yonah,
2102  //@}
2103 
2104  /// \name Netburst
2105  /// Netburst microarchitecture based processors.
2106  //@{
2107  CK_Pentium4,
2108  CK_Pentium4M,
2109  CK_Prescott,
2110  CK_Nocona,
2111  //@}
2112 
2113  /// \name Core
2114  /// Core microarchitecture based processors.
2115  //@{
2116  CK_Core2,
2117 
2118  /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2119  /// codename which GCC no longer accepts as an option to -march, but Clang
2120  /// has some logic for recognizing it.
2121  // FIXME: Warn, deprecate, and potentially remove this.
2122  CK_Penryn,
2123  //@}
2124 
2125  /// \name Atom
2126  /// Atom processors
2127  //@{
2128  CK_Bonnell,
2129  CK_Silvermont,
2130  //@}
2131 
2132  /// \name Nehalem
2133  /// Nehalem microarchitecture based processors.
2134  CK_Nehalem,
2135 
2136  /// \name Westmere
2137  /// Westmere microarchitecture based processors.
2138  CK_Westmere,
2139 
2140  /// \name Sandy Bridge
2141  /// Sandy Bridge microarchitecture based processors.
2142  CK_SandyBridge,
2143 
2144  /// \name Ivy Bridge
2145  /// Ivy Bridge microarchitecture based processors.
2146  CK_IvyBridge,
2147 
2148  /// \name Haswell
2149  /// Haswell microarchitecture based processors.
2150  CK_Haswell,
2151 
2152  /// \name Broadwell
2153  /// Broadwell microarchitecture based processors.
2154  CK_Broadwell,
2155 
2156  /// \name Skylake
2157  /// Skylake microarchitecture based processors.
2158  CK_Skylake,
2159 
2160  /// \name Knights Landing
2161  /// Knights Landing processor.
2162  CK_KNL,
2163 
2164  /// \name K6
2165  /// K6 architecture processors.
2166  //@{
2167  CK_K6,
2168  CK_K6_2,
2169  CK_K6_3,
2170  //@}
2171 
2172  /// \name K7
2173  /// K7 architecture processors.
2174  //@{
2175  CK_Athlon,
2176  CK_AthlonThunderbird,
2177  CK_Athlon4,
2178  CK_AthlonXP,
2179  CK_AthlonMP,
2180  //@}
2181 
2182  /// \name K8
2183  /// K8 architecture processors.
2184  //@{
2185  CK_Athlon64,
2186  CK_Athlon64SSE3,
2187  CK_AthlonFX,
2188  CK_K8,
2189  CK_K8SSE3,
2190  CK_Opteron,
2191  CK_OpteronSSE3,
2192  CK_AMDFAM10,
2193  //@}
2194 
2195  /// \name Bobcat
2196  /// Bobcat architecture processors.
2197  //@{
2198  CK_BTVER1,
2199  CK_BTVER2,
2200  //@}
2201 
2202  /// \name Bulldozer
2203  /// Bulldozer architecture processors.
2204  //@{
2205  CK_BDVER1,
2206  CK_BDVER2,
2207  CK_BDVER3,
2208  CK_BDVER4,
2209  //@}
2210 
2211  /// This specification is deprecated and will be removed in the future.
2212  /// Users should prefer \see CK_K8.
2213  // FIXME: Warn on this when the CPU is set to it.
2214  //@{
2215  CK_x86_64,
2216  //@}
2217 
2218  /// \name Geode
2219  /// Geode processors.
2220  //@{
2221  CK_Geode
2222  //@}
2223  } CPU;
2224 
2225  enum FPMathKind {
2226  FP_Default,
2227  FP_SSE,
2228  FP_387
2229  } FPMath;
2230 
2231 public:
2232  X86TargetInfo(const llvm::Triple &Triple)
2233  : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
2234  XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
2235  HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
2236  HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
2237  HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
2238  HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
2239  HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
2240  HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
2241  BigEndian = false;
2242  LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2243  }
2244  unsigned getFloatEvalMethod() const override {
2245  // X87 evaluates with 80 bits "long double" precision.
2246  return SSELevel == NoSSE ? 2 : 0;
2247  }
2248  void getTargetBuiltins(const Builtin::Info *&Records,
2249  unsigned &NumRecords) const override {
2250  Records = BuiltinInfo;
2252  }
2253  void getGCCRegNames(const char * const *&Names,
2254  unsigned &NumNames) const override {
2255  Names = GCCRegNames;
2256  NumNames = llvm::array_lengthof(GCCRegNames);
2257  }
2258  void getGCCRegAliases(const GCCRegAlias *&Aliases,
2259  unsigned &NumAliases) const override {
2260  Aliases = nullptr;
2261  NumAliases = 0;
2262  }
2263  void getGCCAddlRegNames(const AddlRegName *&Names,
2264  unsigned &NumNames) const override {
2265  Names = AddlRegNames;
2266  NumNames = llvm::array_lengthof(AddlRegNames);
2267  }
2268  bool validateCpuSupports(StringRef Name) const override;
2269  bool validateAsmConstraint(const char *&Name,
2270  TargetInfo::ConstraintInfo &info) const override;
2271 
2272  bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2273 
2274  bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2275 
2276  virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2277 
2278  std::string convertConstraint(const char *&Constraint) const override;
2279  const char *getClobbers() const override {
2280  return "~{dirflag},~{fpsr},~{flags}";
2281  }
2282  void getTargetDefines(const LangOptions &Opts,
2283  MacroBuilder &Builder) const override;
2284  static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2285  bool Enabled);
2286  static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2287  bool Enabled);
2288  static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2289  bool Enabled);
2290  void setFeatureEnabled(llvm::StringMap<bool> &Features,
2291  StringRef Name, bool Enabled) const override {
2292  setFeatureEnabledImpl(Features, Name, Enabled);
2293  }
2294  // This exists purely to cut down on the number of virtual calls in
2295  // getDefaultFeatures which calls this repeatedly.
2296  static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2297  StringRef Name, bool Enabled);
2298  void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2299  bool hasFeature(StringRef Feature) const override;
2300  bool handleTargetFeatures(std::vector<std::string> &Features,
2301  DiagnosticsEngine &Diags) override;
2302  StringRef getABI() const override {
2303  if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2304  return "avx512";
2305  else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2306  return "avx";
2307  else if (getTriple().getArch() == llvm::Triple::x86 &&
2308  MMX3DNowLevel == NoMMX3DNow)
2309  return "no-mmx";
2310  return "";
2311  }
2312  bool setCPU(const std::string &Name) override {
2313  CPU = llvm::StringSwitch<CPUKind>(Name)
2314  .Case("i386", CK_i386)
2315  .Case("i486", CK_i486)
2316  .Case("winchip-c6", CK_WinChipC6)
2317  .Case("winchip2", CK_WinChip2)
2318  .Case("c3", CK_C3)
2319  .Case("i586", CK_i586)
2320  .Case("pentium", CK_Pentium)
2321  .Case("pentium-mmx", CK_PentiumMMX)
2322  .Case("i686", CK_i686)
2323  .Case("pentiumpro", CK_PentiumPro)
2324  .Case("pentium2", CK_Pentium2)
2325  .Case("pentium3", CK_Pentium3)
2326  .Case("pentium3m", CK_Pentium3M)
2327  .Case("pentium-m", CK_PentiumM)
2328  .Case("c3-2", CK_C3_2)
2329  .Case("yonah", CK_Yonah)
2330  .Case("pentium4", CK_Pentium4)
2331  .Case("pentium4m", CK_Pentium4M)
2332  .Case("prescott", CK_Prescott)
2333  .Case("nocona", CK_Nocona)
2334  .Case("core2", CK_Core2)
2335  .Case("penryn", CK_Penryn)
2336  .Case("bonnell", CK_Bonnell)
2337  .Case("atom", CK_Bonnell) // Legacy name.
2338  .Case("silvermont", CK_Silvermont)
2339  .Case("slm", CK_Silvermont) // Legacy name.
2340  .Case("nehalem", CK_Nehalem)
2341  .Case("corei7", CK_Nehalem) // Legacy name.
2342  .Case("westmere", CK_Westmere)
2343  .Case("sandybridge", CK_SandyBridge)
2344  .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2345  .Case("ivybridge", CK_IvyBridge)
2346  .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2347  .Case("haswell", CK_Haswell)
2348  .Case("core-avx2", CK_Haswell) // Legacy name.
2349  .Case("broadwell", CK_Broadwell)
2350  .Case("skylake", CK_Skylake)
2351  .Case("skx", CK_Skylake) // Legacy name.
2352  .Case("knl", CK_KNL)
2353  .Case("k6", CK_K6)
2354  .Case("k6-2", CK_K6_2)
2355  .Case("k6-3", CK_K6_3)
2356  .Case("athlon", CK_Athlon)
2357  .Case("athlon-tbird", CK_AthlonThunderbird)
2358  .Case("athlon-4", CK_Athlon4)
2359  .Case("athlon-xp", CK_AthlonXP)
2360  .Case("athlon-mp", CK_AthlonMP)
2361  .Case("athlon64", CK_Athlon64)
2362  .Case("athlon64-sse3", CK_Athlon64SSE3)
2363  .Case("athlon-fx", CK_AthlonFX)
2364  .Case("k8", CK_K8)
2365  .Case("k8-sse3", CK_K8SSE3)
2366  .Case("opteron", CK_Opteron)
2367  .Case("opteron-sse3", CK_OpteronSSE3)
2368  .Case("barcelona", CK_AMDFAM10)
2369  .Case("amdfam10", CK_AMDFAM10)
2370  .Case("btver1", CK_BTVER1)
2371  .Case("btver2", CK_BTVER2)
2372  .Case("bdver1", CK_BDVER1)
2373  .Case("bdver2", CK_BDVER2)
2374  .Case("bdver3", CK_BDVER3)
2375  .Case("bdver4", CK_BDVER4)
2376  .Case("x86-64", CK_x86_64)
2377  .Case("geode", CK_Geode)
2378  .Default(CK_Generic);
2379 
2380  // Perform any per-CPU checks necessary to determine if this CPU is
2381  // acceptable.
2382  // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2383  // invalid without explaining *why*.
2384  switch (CPU) {
2385  case CK_Generic:
2386  // No processor selected!
2387  return false;
2388 
2389  case CK_i386:
2390  case CK_i486:
2391  case CK_WinChipC6:
2392  case CK_WinChip2:
2393  case CK_C3:
2394  case CK_i586:
2395  case CK_Pentium:
2396  case CK_PentiumMMX:
2397  case CK_i686:
2398  case CK_PentiumPro:
2399  case CK_Pentium2:
2400  case CK_Pentium3:
2401  case CK_Pentium3M:
2402  case CK_PentiumM:
2403  case CK_Yonah:
2404  case CK_C3_2:
2405  case CK_Pentium4:
2406  case CK_Pentium4M:
2407  case CK_Prescott:
2408  case CK_K6:
2409  case CK_K6_2:
2410  case CK_K6_3:
2411  case CK_Athlon:
2412  case CK_AthlonThunderbird:
2413  case CK_Athlon4:
2414  case CK_AthlonXP:
2415  case CK_AthlonMP:
2416  case CK_Geode:
2417  // Only accept certain architectures when compiling in 32-bit mode.
2418  if (getTriple().getArch() != llvm::Triple::x86)
2419  return false;
2420 
2421  // Fallthrough
2422  case CK_Nocona:
2423  case CK_Core2:
2424  case CK_Penryn:
2425  case CK_Bonnell:
2426  case CK_Silvermont:
2427  case CK_Nehalem:
2428  case CK_Westmere:
2429  case CK_SandyBridge:
2430  case CK_IvyBridge:
2431  case CK_Haswell:
2432  case CK_Broadwell:
2433  case CK_Skylake:
2434  case CK_KNL:
2435  case CK_Athlon64:
2436  case CK_Athlon64SSE3:
2437  case CK_AthlonFX:
2438  case CK_K8:
2439  case CK_K8SSE3:
2440  case CK_Opteron:
2441  case CK_OpteronSSE3:
2442  case CK_AMDFAM10:
2443  case CK_BTVER1:
2444  case CK_BTVER2:
2445  case CK_BDVER1:
2446  case CK_BDVER2:
2447  case CK_BDVER3:
2448  case CK_BDVER4:
2449  case CK_x86_64:
2450  return true;
2451  }
2452  llvm_unreachable("Unhandled CPU kind");
2453  }
2454 
2455  bool setFPMath(StringRef Name) override;
2456 
2457  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2458  // We accept all non-ARM calling conventions
2459  return (CC == CC_X86ThisCall ||
2460  CC == CC_X86FastCall ||
2461  CC == CC_X86StdCall ||
2462  CC == CC_X86VectorCall ||
2463  CC == CC_C ||
2464  CC == CC_X86Pascal ||
2465  CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2466  }
2467 
2468  CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2469  return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2470  }
2471 
2472  bool hasSjLjLowering() const override {
2473  return true;
2474  }
2475 };
2476 
2477 bool X86TargetInfo::setFPMath(StringRef Name) {
2478  if (Name == "387") {
2479  FPMath = FP_387;
2480  return true;
2481  }
2482  if (Name == "sse") {
2483  FPMath = FP_SSE;
2484  return true;
2485  }
2486  return false;
2487 }
2488 
2489 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2490  // FIXME: This *really* should not be here.
2491 
2492  // X86_64 always has SSE2.
2493  if (getTriple().getArch() == llvm::Triple::x86_64)
2494  setFeatureEnabledImpl(Features, "sse2", true);
2495 
2496  switch (CPU) {
2497  case CK_Generic:
2498  case CK_i386:
2499  case CK_i486:
2500  case CK_i586:
2501  case CK_Pentium:
2502  case CK_i686:
2503  case CK_PentiumPro:
2504  break;
2505  case CK_PentiumMMX:
2506  case CK_Pentium2:
2507  case CK_K6:
2508  case CK_WinChipC6:
2509  setFeatureEnabledImpl(Features, "mmx", true);
2510  break;
2511  case CK_Pentium3:
2512  case CK_Pentium3M:
2513  case CK_C3_2:
2514  setFeatureEnabledImpl(Features, "sse", true);
2515  break;
2516  case CK_PentiumM:
2517  case CK_Pentium4:
2518  case CK_Pentium4M:
2519  case CK_x86_64:
2520  setFeatureEnabledImpl(Features, "sse2", true);
2521  break;
2522  case CK_Yonah:
2523  case CK_Prescott:
2524  case CK_Nocona:
2525  setFeatureEnabledImpl(Features, "sse3", true);
2526  setFeatureEnabledImpl(Features, "cx16", true);
2527  break;
2528  case CK_Core2:
2529  case CK_Bonnell:
2530  setFeatureEnabledImpl(Features, "ssse3", true);
2531  setFeatureEnabledImpl(Features, "cx16", true);
2532  break;
2533  case CK_Penryn:
2534  setFeatureEnabledImpl(Features, "sse4.1", true);
2535  setFeatureEnabledImpl(Features, "cx16", true);
2536  break;
2537  case CK_Skylake:
2538  setFeatureEnabledImpl(Features, "avx512f", true);
2539  setFeatureEnabledImpl(Features, "avx512cd", true);
2540  setFeatureEnabledImpl(Features, "avx512dq", true);
2541  setFeatureEnabledImpl(Features, "avx512bw", true);
2542  setFeatureEnabledImpl(Features, "avx512vl", true);
2543  // FALLTHROUGH
2544  case CK_Broadwell:
2545  setFeatureEnabledImpl(Features, "rdseed", true);
2546  setFeatureEnabledImpl(Features, "adx", true);
2547  // FALLTHROUGH
2548  case CK_Haswell:
2549  setFeatureEnabledImpl(Features, "avx2", true);
2550  setFeatureEnabledImpl(Features, "lzcnt", true);
2551  setFeatureEnabledImpl(Features, "bmi", true);
2552  setFeatureEnabledImpl(Features, "bmi2", true);
2553  setFeatureEnabledImpl(Features, "rtm", true);
2554  setFeatureEnabledImpl(Features, "fma", true);
2555  // FALLTHROUGH
2556  case CK_IvyBridge:
2557  setFeatureEnabledImpl(Features, "rdrnd", true);
2558  setFeatureEnabledImpl(Features, "f16c", true);
2559  setFeatureEnabledImpl(Features, "fsgsbase", true);
2560  // FALLTHROUGH
2561  case CK_SandyBridge:
2562  setFeatureEnabledImpl(Features, "avx", true);
2563  // FALLTHROUGH
2564  case CK_Westmere:
2565  case CK_Silvermont:
2566  setFeatureEnabledImpl(Features, "aes", true);
2567  setFeatureEnabledImpl(Features, "pclmul", true);
2568  // FALLTHROUGH
2569  case CK_Nehalem:
2570  setFeatureEnabledImpl(Features, "sse4.2", true);
2571  setFeatureEnabledImpl(Features, "cx16", true);
2572  break;
2573  case CK_KNL:
2574  setFeatureEnabledImpl(Features, "avx512f", true);
2575  setFeatureEnabledImpl(Features, "avx512cd", true);
2576  setFeatureEnabledImpl(Features, "avx512er", true);
2577  setFeatureEnabledImpl(Features, "avx512pf", true);
2578  setFeatureEnabledImpl(Features, "rdseed", true);
2579  setFeatureEnabledImpl(Features, "adx", true);
2580  setFeatureEnabledImpl(Features, "lzcnt", true);
2581  setFeatureEnabledImpl(Features, "bmi", true);
2582  setFeatureEnabledImpl(Features, "bmi2", true);
2583  setFeatureEnabledImpl(Features, "rtm", true);
2584  setFeatureEnabledImpl(Features, "fma", true);
2585  setFeatureEnabledImpl(Features, "rdrnd", true);
2586  setFeatureEnabledImpl(Features, "f16c", true);
2587  setFeatureEnabledImpl(Features, "fsgsbase", true);
2588  setFeatureEnabledImpl(Features, "aes", true);
2589  setFeatureEnabledImpl(Features, "pclmul", true);
2590  setFeatureEnabledImpl(Features, "cx16", true);
2591  break;
2592  case CK_K6_2:
2593  case CK_K6_3:
2594  case CK_WinChip2:
2595  case CK_C3:
2596  setFeatureEnabledImpl(Features, "3dnow", true);
2597  break;
2598  case CK_Athlon:
2599  case CK_AthlonThunderbird:
2600  case CK_Geode:
2601  setFeatureEnabledImpl(Features, "3dnowa", true);
2602  break;
2603  case CK_Athlon4:
2604  case CK_AthlonXP:
2605  case CK_AthlonMP:
2606  setFeatureEnabledImpl(Features, "sse", true);
2607  setFeatureEnabledImpl(Features, "3dnowa", true);
2608  break;
2609  case CK_K8:
2610  case CK_Opteron:
2611  case CK_Athlon64:
2612  case CK_AthlonFX:
2613  setFeatureEnabledImpl(Features, "sse2", true);
2614  setFeatureEnabledImpl(Features, "3dnowa", true);
2615  break;
2616  case CK_AMDFAM10:
2617  setFeatureEnabledImpl(Features, "sse4a", true);
2618  setFeatureEnabledImpl(Features, "lzcnt", true);
2619  setFeatureEnabledImpl(Features, "popcnt", true);
2620  // FALLTHROUGH
2621  case CK_K8SSE3:
2622  case CK_OpteronSSE3:
2623  case CK_Athlon64SSE3:
2624  setFeatureEnabledImpl(Features, "sse3", true);
2625  setFeatureEnabledImpl(Features, "3dnowa", true);
2626  break;
2627  case CK_BTVER2:
2628  setFeatureEnabledImpl(Features, "avx", true);
2629  setFeatureEnabledImpl(Features, "aes", true);
2630  setFeatureEnabledImpl(Features, "pclmul", true);
2631  setFeatureEnabledImpl(Features, "bmi", true);
2632  setFeatureEnabledImpl(Features, "f16c", true);
2633  // FALLTHROUGH
2634  case CK_BTVER1:
2635  setFeatureEnabledImpl(Features, "ssse3", true);
2636  setFeatureEnabledImpl(Features, "sse4a", true);
2637  setFeatureEnabledImpl(Features, "lzcnt", true);
2638  setFeatureEnabledImpl(Features, "popcnt", true);
2639  setFeatureEnabledImpl(Features, "prfchw", true);
2640  setFeatureEnabledImpl(Features, "cx16", true);
2641  break;
2642  case CK_BDVER4:
2643  setFeatureEnabledImpl(Features, "avx2", true);
2644  setFeatureEnabledImpl(Features, "bmi2", true);
2645  // FALLTHROUGH
2646  case CK_BDVER3:
2647  setFeatureEnabledImpl(Features, "fsgsbase", true);
2648  // FALLTHROUGH
2649  case CK_BDVER2:
2650  setFeatureEnabledImpl(Features, "bmi", true);
2651  setFeatureEnabledImpl(Features, "fma", true);
2652  setFeatureEnabledImpl(Features, "f16c", true);
2653  setFeatureEnabledImpl(Features, "tbm", true);
2654  // FALLTHROUGH
2655  case CK_BDVER1:
2656  // xop implies avx, sse4a and fma4.
2657  setFeatureEnabledImpl(Features, "xop", true);
2658  setFeatureEnabledImpl(Features, "lzcnt", true);
2659  setFeatureEnabledImpl(Features, "aes", true);
2660  setFeatureEnabledImpl(Features, "pclmul", true);
2661  setFeatureEnabledImpl(Features, "prfchw", true);
2662  setFeatureEnabledImpl(Features, "cx16", true);
2663  break;
2664  }
2665 }
2666 
2667 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2668  X86SSEEnum Level, bool Enabled) {
2669  if (Enabled) {
2670  switch (Level) {
2671  case AVX512F:
2672  Features["avx512f"] = true;
2673  case AVX2:
2674  Features["avx2"] = true;
2675  case AVX:
2676  Features["avx"] = true;
2677  case SSE42:
2678  Features["sse4.2"] = true;
2679  case SSE41:
2680  Features["sse4.1"] = true;
2681  case SSSE3:
2682  Features["ssse3"] = true;
2683  case SSE3:
2684  Features["sse3"] = true;
2685  case SSE2:
2686  Features["sse2"] = true;
2687  case SSE1:
2688  Features["sse"] = true;
2689  case NoSSE:
2690  break;
2691  }
2692  return;
2693  }
2694 
2695  switch (Level) {
2696  case NoSSE:
2697  case SSE1:
2698  Features["sse"] = false;
2699  case SSE2:
2700  Features["sse2"] = Features["pclmul"] = Features["aes"] =
2701  Features["sha"] = false;
2702  case SSE3:
2703  Features["sse3"] = false;
2704  setXOPLevel(Features, NoXOP, false);
2705  case SSSE3:
2706  Features["ssse3"] = false;
2707  case SSE41:
2708  Features["sse4.1"] = false;
2709  case SSE42:
2710  Features["sse4.2"] = false;
2711  case AVX:
2712  Features["fma"] = Features["avx"] = Features["f16c"] = false;
2713  setXOPLevel(Features, FMA4, false);
2714  case AVX2:
2715  Features["avx2"] = false;
2716  case AVX512F:
2717  Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2718  Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2719  Features["avx512vl"] = false;
2720  }
2721 }
2722 
2723 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2724  MMX3DNowEnum Level, bool Enabled) {
2725  if (Enabled) {
2726  switch (Level) {
2727  case AMD3DNowAthlon:
2728  Features["3dnowa"] = true;
2729  case AMD3DNow:
2730  Features["3dnow"] = true;
2731  case MMX:
2732  Features["mmx"] = true;
2733  case NoMMX3DNow:
2734  break;
2735  }
2736  return;
2737  }
2738 
2739  switch (Level) {
2740  case NoMMX3DNow:
2741  case MMX:
2742  Features["mmx"] = false;
2743  case AMD3DNow:
2744  Features["3dnow"] = false;
2745  case AMD3DNowAthlon:
2746  Features["3dnowa"] = false;
2747  }
2748 }
2749 
2750 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2751  bool Enabled) {
2752  if (Enabled) {
2753  switch (Level) {
2754  case XOP:
2755  Features["xop"] = true;
2756  case FMA4:
2757  Features["fma4"] = true;
2758  setSSELevel(Features, AVX, true);
2759  case SSE4A:
2760  Features["sse4a"] = true;
2761  setSSELevel(Features, SSE3, true);
2762  case NoXOP:
2763  break;
2764  }
2765  return;
2766  }
2767 
2768  switch (Level) {
2769  case NoXOP:
2770  case SSE4A:
2771  Features["sse4a"] = false;
2772  case FMA4:
2773  Features["fma4"] = false;
2774  case XOP:
2775  Features["xop"] = false;
2776  }
2777 }
2778 
2779 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2780  StringRef Name, bool Enabled) {
2781  // This is a bit of a hack to deal with the sse4 target feature when used
2782  // as part of the target attribute. We handle sse4 correctly everywhere
2783  // else. See below for more information on how we handle the sse4 options.
2784  if (Name != "sse4")
2785  Features[Name] = Enabled;
2786 
2787  if (Name == "mmx") {
2788  setMMXLevel(Features, MMX, Enabled);
2789  } else if (Name == "sse") {
2790  setSSELevel(Features, SSE1, Enabled);
2791  } else if (Name == "sse2") {
2792  setSSELevel(Features, SSE2, Enabled);
2793  } else if (Name == "sse3") {
2794  setSSELevel(Features, SSE3, Enabled);
2795  } else if (Name == "ssse3") {
2796  setSSELevel(Features, SSSE3, Enabled);
2797  } else if (Name == "sse4.2") {
2798  setSSELevel(Features, SSE42, Enabled);
2799  } else if (Name == "sse4.1") {
2800  setSSELevel(Features, SSE41, Enabled);
2801  } else if (Name == "3dnow") {
2802  setMMXLevel(Features, AMD3DNow, Enabled);
2803  } else if (Name == "3dnowa") {
2804  setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2805  } else if (Name == "aes") {
2806  if (Enabled)
2807  setSSELevel(Features, SSE2, Enabled);
2808  } else if (Name == "pclmul") {
2809  if (Enabled)
2810  setSSELevel(Features, SSE2, Enabled);
2811  } else if (Name == "avx") {
2812  setSSELevel(Features, AVX, Enabled);
2813  } else if (Name == "avx2") {
2814  setSSELevel(Features, AVX2, Enabled);
2815  } else if (Name == "avx512f") {
2816  setSSELevel(Features, AVX512F, Enabled);
2817  } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2818  || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2819  if (Enabled)
2820  setSSELevel(Features, AVX512F, Enabled);
2821  } else if (Name == "fma") {
2822  if (Enabled)
2823  setSSELevel(Features, AVX, Enabled);
2824  } else if (Name == "fma4") {
2825  setXOPLevel(Features, FMA4, Enabled);
2826  } else if (Name == "xop") {
2827  setXOPLevel(Features, XOP, Enabled);
2828  } else if (Name == "sse4a") {
2829  setXOPLevel(Features, SSE4A, Enabled);
2830  } else if (Name == "f16c") {
2831  if (Enabled)
2832  setSSELevel(Features, AVX, Enabled);
2833  } else if (Name == "sha") {
2834  if (Enabled)
2835  setSSELevel(Features, SSE2, Enabled);
2836  } else if (Name == "sse4") {
2837  // We can get here via the __target__ attribute since that's not controlled
2838  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
2839  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
2840  // disabled.
2841  if (Enabled)
2842  setSSELevel(Features, SSE42, Enabled);
2843  else
2844  setSSELevel(Features, SSE41, Enabled);
2845  }
2846 }
2847 
2848 /// handleTargetFeatures - Perform initialization based on the user
2849 /// configured set of features.
2850 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2851  DiagnosticsEngine &Diags) {
2852  // Remember the maximum enabled sselevel.
2853  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2854  // Ignore disabled features.
2855  if (Features[i][0] == '-')
2856  continue;
2857 
2858  StringRef Feature = StringRef(Features[i]).substr(1);
2859 
2860  if (Feature == "aes") {
2861  HasAES = true;
2862  continue;
2863  }
2864 
2865  if (Feature == "pclmul") {
2866  HasPCLMUL = true;
2867  continue;
2868  }
2869 
2870  if (Feature == "lzcnt") {
2871  HasLZCNT = true;
2872  continue;
2873  }
2874 
2875  if (Feature == "rdrnd") {
2876  HasRDRND = true;
2877  continue;
2878  }
2879 
2880  if (Feature == "fsgsbase") {
2881  HasFSGSBASE = true;
2882  continue;
2883  }
2884 
2885  if (Feature == "bmi") {
2886  HasBMI = true;
2887  continue;
2888  }
2889 
2890  if (Feature == "bmi2") {
2891  HasBMI2 = true;
2892  continue;
2893  }
2894 
2895  if (Feature == "popcnt") {
2896  HasPOPCNT = true;
2897  continue;
2898  }
2899 
2900  if (Feature == "rtm") {
2901  HasRTM = true;
2902  continue;
2903  }
2904 
2905  if (Feature == "prfchw") {
2906  HasPRFCHW = true;
2907  continue;
2908  }
2909 
2910  if (Feature == "rdseed") {
2911  HasRDSEED = true;
2912  continue;
2913  }
2914 
2915  if (Feature == "adx") {
2916  HasADX = true;
2917  continue;
2918  }
2919 
2920  if (Feature == "tbm") {
2921  HasTBM = true;
2922  continue;
2923  }
2924 
2925  if (Feature == "fma") {
2926  HasFMA = true;
2927  continue;
2928  }
2929 
2930  if (Feature == "f16c") {
2931  HasF16C = true;
2932  continue;
2933  }
2934 
2935  if (Feature == "avx512cd") {
2936  HasAVX512CD = true;
2937  continue;
2938  }
2939 
2940  if (Feature == "avx512er") {
2941  HasAVX512ER = true;
2942  continue;
2943  }
2944 
2945  if (Feature == "avx512pf") {
2946  HasAVX512PF = true;
2947  continue;
2948  }
2949 
2950  if (Feature == "avx512dq") {
2951  HasAVX512DQ = true;
2952  continue;
2953  }
2954 
2955  if (Feature == "avx512bw") {
2956  HasAVX512BW = true;
2957  continue;
2958  }
2959 
2960  if (Feature == "avx512vl") {
2961  HasAVX512VL = true;
2962  continue;
2963  }
2964 
2965  if (Feature == "sha") {
2966  HasSHA = true;
2967  continue;
2968  }
2969 
2970  if (Feature == "cx16") {
2971  HasCX16 = true;
2972  continue;
2973  }
2974 
2975  assert(Features[i][0] == '+' && "Invalid target feature!");
2976  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2977  .Case("avx512f", AVX512F)
2978  .Case("avx2", AVX2)
2979  .Case("avx", AVX)
2980  .Case("sse4.2", SSE42)
2981  .Case("sse4.1", SSE41)
2982  .Case("ssse3", SSSE3)
2983  .Case("sse3", SSE3)
2984  .Case("sse2", SSE2)
2985  .Case("sse", SSE1)
2986  .Default(NoSSE);
2987  SSELevel = std::max(SSELevel, Level);
2988 
2989  MMX3DNowEnum ThreeDNowLevel =
2990  llvm::StringSwitch<MMX3DNowEnum>(Feature)
2991  .Case("3dnowa", AMD3DNowAthlon)
2992  .Case("3dnow", AMD3DNow)
2993  .Case("mmx", MMX)
2994  .Default(NoMMX3DNow);
2995  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2996 
2997  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2998  .Case("xop", XOP)
2999  .Case("fma4", FMA4)
3000  .Case("sse4a", SSE4A)
3001  .Default(NoXOP);
3002  XOPLevel = std::max(XOPLevel, XLevel);
3003  }
3004 
3005  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
3006  // Can't do this earlier because we need to be able to explicitly enable
3007  // popcnt and still disable sse4.2.
3008  if (!HasPOPCNT && SSELevel >= SSE42 &&
3009  std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
3010  HasPOPCNT = true;
3011  Features.push_back("+popcnt");
3012  }
3013 
3014  // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
3015  if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
3016  std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
3017  HasPRFCHW = true;
3018  Features.push_back("+prfchw");
3019  }
3020 
3021  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3022  // matches the selected sse level.
3023  if (FPMath == FP_SSE && SSELevel < SSE1) {
3024  Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
3025  return false;
3026  } else if (FPMath == FP_387 && SSELevel >= SSE1) {
3027  Diags.Report(diag::err_target_unsupported_fpmath) << "387";
3028  return false;
3029  }
3030 
3031  // Don't tell the backend if we're turning off mmx; it will end up disabling
3032  // SSE, which we don't want.
3033  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
3034  // then enable MMX.
3035  std::vector<std::string>::iterator it;
3036  it = std::find(Features.begin(), Features.end(), "-mmx");
3037  if (it != Features.end())
3038  Features.erase(it);
3039  else if (SSELevel > NoSSE)
3040  MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
3041 
3042  SimdDefaultAlign =
3043  (getABI() == "avx512") ? 512 : (getABI() == "avx") ? 256 : 128;
3044  return true;
3045 }
3046 
3047 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3048 /// definitions for this particular subtarget.
3049 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3050  MacroBuilder &Builder) const {
3051  // Target identification.
3052  if (getTriple().getArch() == llvm::Triple::x86_64) {
3053  Builder.defineMacro("__amd64__");
3054  Builder.defineMacro("__amd64");
3055  Builder.defineMacro("__x86_64");
3056  Builder.defineMacro("__x86_64__");
3057  if (getTriple().getArchName() == "x86_64h") {
3058  Builder.defineMacro("__x86_64h");
3059  Builder.defineMacro("__x86_64h__");
3060  }
3061  } else {
3062  DefineStd(Builder, "i386", Opts);
3063  }
3064 
3065  // Subtarget options.
3066  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3067  // truly should be based on -mtune options.
3068  switch (CPU) {
3069  case CK_Generic:
3070  break;
3071  case CK_i386:
3072  // The rest are coming from the i386 define above.
3073  Builder.defineMacro("__tune_i386__");
3074  break;
3075  case CK_i486:
3076  case CK_WinChipC6:
3077  case CK_WinChip2:
3078  case CK_C3:
3079  defineCPUMacros(Builder, "i486");
3080  break;
3081  case CK_PentiumMMX:
3082  Builder.defineMacro("__pentium_mmx__");
3083  Builder.defineMacro("__tune_pentium_mmx__");
3084  // Fallthrough
3085  case CK_i586:
3086  case CK_Pentium:
3087  defineCPUMacros(Builder, "i586");
3088  defineCPUMacros(Builder, "pentium");
3089  break;
3090  case CK_Pentium3:
3091  case CK_Pentium3M:
3092  case CK_PentiumM:
3093  Builder.defineMacro("__tune_pentium3__");
3094  // Fallthrough
3095  case CK_Pentium2:
3096  case CK_C3_2:
3097  Builder.defineMacro("__tune_pentium2__");
3098  // Fallthrough
3099  case CK_PentiumPro:
3100  Builder.defineMacro("__tune_i686__");
3101  Builder.defineMacro("__tune_pentiumpro__");
3102  // Fallthrough
3103  case CK_i686:
3104  Builder.defineMacro("__i686");
3105  Builder.defineMacro("__i686__");
3106  // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3107  Builder.defineMacro("__pentiumpro");
3108  Builder.defineMacro("__pentiumpro__");
3109  break;
3110  case CK_Pentium4:
3111  case CK_Pentium4M:
3112  defineCPUMacros(Builder, "pentium4");
3113  break;
3114  case CK_Yonah:
3115  case CK_Prescott:
3116  case CK_Nocona:
3117  defineCPUMacros(Builder, "nocona");
3118  break;
3119  case CK_Core2:
3120  case CK_Penryn:
3121  defineCPUMacros(Builder, "core2");
3122  break;
3123  case CK_Bonnell:
3124  defineCPUMacros(Builder, "atom");
3125  break;
3126  case CK_Silvermont:
3127  defineCPUMacros(Builder, "slm");
3128  break;
3129  case CK_Nehalem:
3130  case CK_Westmere:
3131  case CK_SandyBridge:
3132  case CK_IvyBridge:
3133  case CK_Haswell:
3134  case CK_Broadwell:
3135  // FIXME: Historically, we defined this legacy name, it would be nice to
3136  // remove it at some point. We've never exposed fine-grained names for
3137  // recent primary x86 CPUs, and we should keep it that way.
3138  defineCPUMacros(Builder, "corei7");
3139  break;
3140  case CK_Skylake:
3141  // FIXME: Historically, we defined this legacy name, it would be nice to
3142  // remove it at some point. This is the only fine-grained CPU macro in the
3143  // main intel CPU line, and it would be better to not have these and force
3144  // people to use ISA macros.
3145  defineCPUMacros(Builder, "skx");
3146  break;
3147  case CK_KNL:
3148  defineCPUMacros(Builder, "knl");
3149  break;
3150  case CK_K6_2:
3151  Builder.defineMacro("__k6_2__");
3152  Builder.defineMacro("__tune_k6_2__");
3153  // Fallthrough
3154  case CK_K6_3:
3155  if (CPU != CK_K6_2) { // In case of fallthrough
3156  // FIXME: GCC may be enabling these in cases where some other k6
3157  // architecture is specified but -m3dnow is explicitly provided. The
3158  // exact semantics need to be determined and emulated here.
3159  Builder.defineMacro("__k6_3__");
3160  Builder.defineMacro("__tune_k6_3__");
3161  }
3162  // Fallthrough
3163  case CK_K6:
3164  defineCPUMacros(Builder, "k6");
3165  break;
3166  case CK_Athlon:
3167  case CK_AthlonThunderbird:
3168  case CK_Athlon4:
3169  case CK_AthlonXP:
3170  case CK_AthlonMP:
3171  defineCPUMacros(Builder, "athlon");
3172  if (SSELevel != NoSSE) {
3173  Builder.defineMacro("__athlon_sse__");
3174  Builder.defineMacro("__tune_athlon_sse__");
3175  }
3176  break;
3177  case CK_K8:
3178  case CK_K8SSE3:
3179  case CK_x86_64:
3180  case CK_Opteron:
3181  case CK_OpteronSSE3:
3182  case CK_Athlon64:
3183  case CK_Athlon64SSE3:
3184  case CK_AthlonFX:
3185  defineCPUMacros(Builder, "k8");
3186  break;
3187  case CK_AMDFAM10:
3188  defineCPUMacros(Builder, "amdfam10");
3189  break;
3190  case CK_BTVER1:
3191  defineCPUMacros(Builder, "btver1");
3192  break;
3193  case CK_BTVER2:
3194  defineCPUMacros(Builder, "btver2");
3195  break;
3196  case CK_BDVER1:
3197  defineCPUMacros(Builder, "bdver1");
3198  break;
3199  case CK_BDVER2:
3200  defineCPUMacros(Builder, "bdver2");
3201  break;
3202  case CK_BDVER3:
3203  defineCPUMacros(Builder, "bdver3");
3204  break;
3205  case CK_BDVER4:
3206  defineCPUMacros(Builder, "bdver4");
3207  break;
3208  case CK_Geode:
3209  defineCPUMacros(Builder, "geode");
3210  break;
3211  }
3212 
3213  // Target properties.
3214  Builder.defineMacro("__REGISTER_PREFIX__", "");
3215 
3216  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3217  // functions in glibc header files that use FP Stack inline asm which the
3218  // backend can't deal with (PR879).
3219  Builder.defineMacro("__NO_MATH_INLINES");
3220 
3221  if (HasAES)
3222  Builder.defineMacro("__AES__");
3223 
3224  if (HasPCLMUL)
3225  Builder.defineMacro("__PCLMUL__");
3226 
3227  if (HasLZCNT)
3228  Builder.defineMacro("__LZCNT__");
3229 
3230  if (HasRDRND)
3231  Builder.defineMacro("__RDRND__");
3232 
3233  if (HasFSGSBASE)
3234  Builder.defineMacro("__FSGSBASE__");
3235 
3236  if (HasBMI)
3237  Builder.defineMacro("__BMI__");
3238 
3239  if (HasBMI2)
3240  Builder.defineMacro("__BMI2__");
3241 
3242  if (HasPOPCNT)
3243  Builder.defineMacro("__POPCNT__");
3244 
3245  if (HasRTM)
3246  Builder.defineMacro("__RTM__");
3247 
3248  if (HasPRFCHW)
3249  Builder.defineMacro("__PRFCHW__");
3250 
3251  if (HasRDSEED)
3252  Builder.defineMacro("__RDSEED__");
3253 
3254  if (HasADX)
3255  Builder.defineMacro("__ADX__");
3256 
3257  if (HasTBM)
3258  Builder.defineMacro("__TBM__");
3259 
3260  switch (XOPLevel) {
3261  case XOP:
3262  Builder.defineMacro("__XOP__");
3263  case FMA4:
3264  Builder.defineMacro("__FMA4__");
3265  case SSE4A:
3266  Builder.defineMacro("__SSE4A__");
3267  case NoXOP:
3268  break;
3269  }
3270 
3271  if (HasFMA)
3272  Builder.defineMacro("__FMA__");
3273 
3274  if (HasF16C)
3275  Builder.defineMacro("__F16C__");
3276 
3277  if (HasAVX512CD)
3278  Builder.defineMacro("__AVX512CD__");
3279  if (HasAVX512ER)
3280  Builder.defineMacro("__AVX512ER__");
3281  if (HasAVX512PF)
3282  Builder.defineMacro("__AVX512PF__");
3283  if (HasAVX512DQ)
3284  Builder.defineMacro("__AVX512DQ__");
3285  if (HasAVX512BW)
3286  Builder.defineMacro("__AVX512BW__");
3287  if (HasAVX512VL)
3288  Builder.defineMacro("__AVX512VL__");
3289 
3290  if (HasSHA)
3291  Builder.defineMacro("__SHA__");
3292 
3293  if (HasCX16)
3294  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3295 
3296  // Each case falls through to the previous one here.
3297  switch (SSELevel) {
3298  case AVX512F:
3299  Builder.defineMacro("__AVX512F__");
3300  case AVX2:
3301  Builder.defineMacro("__AVX2__");
3302  case AVX:
3303  Builder.defineMacro("__AVX__");
3304  case SSE42:
3305  Builder.defineMacro("__SSE4_2__");
3306  case SSE41:
3307  Builder.defineMacro("__SSE4_1__");
3308  case SSSE3:
3309  Builder.defineMacro("__SSSE3__");
3310  case SSE3:
3311  Builder.defineMacro("__SSE3__");
3312  case SSE2:
3313  Builder.defineMacro("__SSE2__");
3314  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3315  case SSE1:
3316  Builder.defineMacro("__SSE__");
3317  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3318  case NoSSE:
3319  break;
3320  }
3321 
3322  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3323  switch (SSELevel) {
3324  case AVX512F:
3325  case AVX2:
3326  case AVX:
3327  case SSE42:
3328  case SSE41:
3329  case SSSE3:
3330  case SSE3:
3331  case SSE2:
3332  Builder.defineMacro("_M_IX86_FP", Twine(2));
3333  break;
3334  case SSE1:
3335  Builder.defineMacro("_M_IX86_FP", Twine(1));
3336  break;
3337  default:
3338  Builder.defineMacro("_M_IX86_FP", Twine(0));
3339  }
3340  }
3341 
3342  // Each case falls through to the previous one here.
3343  switch (MMX3DNowLevel) {
3344  case AMD3DNowAthlon:
3345  Builder.defineMacro("__3dNOW_A__");
3346  case AMD3DNow:
3347  Builder.defineMacro("__3dNOW__");
3348  case MMX:
3349  Builder.defineMacro("__MMX__");
3350  case NoMMX3DNow:
3351  break;
3352  }
3353 
3354  if (CPU >= CK_i486) {
3355  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3356  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3357  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3358  }
3359  if (CPU >= CK_i586)
3360  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3361 }
3362 
3363 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3364  return llvm::StringSwitch<bool>(Feature)
3365  .Case("aes", HasAES)
3366  .Case("avx", SSELevel >= AVX)
3367  .Case("avx2", SSELevel >= AVX2)
3368  .Case("avx512f", SSELevel >= AVX512F)
3369  .Case("avx512cd", HasAVX512CD)
3370  .Case("avx512er", HasAVX512ER)
3371  .Case("avx512pf", HasAVX512PF)
3372  .Case("avx512dq", HasAVX512DQ)
3373  .Case("avx512bw", HasAVX512BW)
3374  .Case("avx512vl", HasAVX512VL)
3375  .Case("bmi", HasBMI)
3376  .Case("bmi2", HasBMI2)
3377  .Case("cx16", HasCX16)
3378  .Case("f16c", HasF16C)
3379  .Case("fma", HasFMA)
3380  .Case("fma4", XOPLevel >= FMA4)
3381  .Case("fsgsbase", HasFSGSBASE)
3382  .Case("lzcnt", HasLZCNT)
3383  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3384  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3385  .Case("mmx", MMX3DNowLevel >= MMX)
3386  .Case("pclmul", HasPCLMUL)
3387  .Case("popcnt", HasPOPCNT)
3388  .Case("prfchw", HasPRFCHW)
3389  .Case("rdrnd", HasRDRND)
3390  .Case("rdseed", HasRDSEED)
3391  .Case("rtm", HasRTM)
3392  .Case("sha", HasSHA)
3393  .Case("sse", SSELevel >= SSE1)
3394  .Case("sse2", SSELevel >= SSE2)
3395  .Case("sse3", SSELevel >= SSE3)
3396  .Case("ssse3", SSELevel >= SSSE3)
3397  .Case("sse4.1", SSELevel >= SSE41)
3398  .Case("sse4.2", SSELevel >= SSE42)
3399  .Case("sse4a", XOPLevel >= SSE4A)
3400  .Case("tbm", HasTBM)
3401  .Case("x86", true)
3402  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3403  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3404  .Case("xop", XOPLevel >= XOP)
3405  .Default(false);
3406 }
3407 
3408 // We can't use a generic validation scheme for the features accepted here
3409 // versus subtarget features accepted in the target attribute because the
3410 // bitfield structure that's initialized in the runtime only supports the
3411 // below currently rather than the full range of subtarget features. (See
3412 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
3413 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
3414  return llvm::StringSwitch<bool>(FeatureStr)
3415  .Case("cmov", true)
3416  .Case("mmx", true)
3417  .Case("popcnt", true)
3418  .Case("sse", true)
3419  .Case("sse2", true)
3420  .Case("sse3", true)
3421  .Case("sse4.1", true)
3422  .Case("sse4.2", true)
3423  .Case("avx", true)
3424  .Case("avx2", true)
3425  .Case("sse4a", true)
3426  .Case("fma4", true)
3427  .Case("xop", true)
3428  .Case("fma", true)
3429  .Case("avx512f", true)
3430  .Case("bmi", true)
3431  .Case("bmi2", true)
3432  .Default(false);
3433 }
3434 
3435 bool
3436 X86TargetInfo::validateAsmConstraint(const char *&Name,
3437  TargetInfo::ConstraintInfo &Info) const {
3438  switch (*Name) {
3439  default: return false;
3440  case 'I':
3441  Info.setRequiresImmediate(0, 31);
3442  return true;
3443  case 'J':
3444  Info.setRequiresImmediate(0, 63);
3445  return true;
3446  case 'K':
3447  Info.setRequiresImmediate(-128, 127);
3448  return true;
3449  case 'L':
3450  // FIXME: properly analyze this constraint:
3451  // must be one of 0xff, 0xffff, or 0xffffffff
3452  return true;
3453  case 'M':
3454  Info.setRequiresImmediate(0, 3);
3455  return true;
3456  case 'N':
3457  Info.setRequiresImmediate(0, 255);
3458  return true;
3459  case 'O':
3460  Info.setRequiresImmediate(0, 127);
3461  return true;
3462  case 'Y': // first letter of a pair:
3463  switch (*(Name+1)) {
3464  default: return false;
3465  case '0': // First SSE register.
3466  case 't': // Any SSE register, when SSE2 is enabled.
3467  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3468  case 'm': // any MMX register, when inter-unit moves enabled.
3469  break; // falls through to setAllowsRegister.
3470  }
3471  case 'f': // any x87 floating point stack register.
3472  // Constraint 'f' cannot be used for output operands.
3473  if (Info.ConstraintStr[0] == '=')
3474  return false;
3475 
3476  Info.setAllowsRegister();
3477  return true;
3478  case 'a': // eax.
3479  case 'b': // ebx.
3480  case 'c': // ecx.
3481  case 'd': // edx.
3482  case 'S': // esi.
3483  case 'D': // edi.
3484  case 'A': // edx:eax.
3485  case 't': // top of floating point stack.
3486  case 'u': // second from top of floating point stack.
3487  case 'q': // Any register accessible as [r]l: a, b, c, and d.
3488  case 'y': // Any MMX register.
3489  case 'x': // Any SSE register.
3490  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3491  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3492  case 'l': // "Index" registers: any general register that can be used as an
3493  // index in a base+index memory access.
3494  Info.setAllowsRegister();
3495  return true;
3496  case 'C': // SSE floating point constant.
3497  case 'G': // x87 floating point constant.
3498  case 'e': // 32-bit signed integer constant for use with zero-extending
3499  // x86_64 instructions.
3500  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3501  // x86_64 instructions.
3502  return true;
3503  }
3504 }
3505 
3506 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3507  unsigned Size) const {
3508  // Strip off constraint modifiers.
3509  while (Constraint[0] == '=' ||
3510  Constraint[0] == '+' ||
3511  Constraint[0] == '&')
3512  Constraint = Constraint.substr(1);
3513 
3514  return validateOperandSize(Constraint, Size);
3515 }
3516 
3517 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3518  unsigned Size) const {
3519  return validateOperandSize(Constraint, Size);
3520 }
3521 
3522 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3523  unsigned Size) const {
3524  switch (Constraint[0]) {
3525  default: break;
3526  case 'y':
3527  return Size <= 64;
3528  case 'f':
3529  case 't':
3530  case 'u':
3531  return Size <= 128;
3532  case 'x':
3533  // 256-bit ymm registers can be used if target supports AVX.
3534  return Size <= (SSELevel >= AVX ? 256U : 128U);
3535  }
3536 
3537  return true;
3538 }
3539 
3540 std::string
3541 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3542  switch (*Constraint) {
3543  case 'a': return std::string("{ax}");
3544  case 'b': return std::string("{bx}");
3545  case 'c': return std::string("{cx}");
3546  case 'd': return std::string("{dx}");
3547  case 'S': return std::string("{si}");
3548  case 'D': return std::string("{di}");
3549  case 'p': // address
3550  return std::string("im");
3551  case 't': // top of floating point stack.
3552  return std::string("{st}");
3553  case 'u': // second from top of floating point stack.
3554  return std::string("{st(1)}"); // second from top of floating point stack.
3555  default:
3556  return std::string(1, *Constraint);
3557  }
3558 }
3559 
3560 // X86-32 generic target
3561 class X86_32TargetInfo : public X86TargetInfo {
3562 public:
3563  X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3564  DoubleAlign = LongLongAlign = 32;
3565  LongDoubleWidth = 96;
3566  LongDoubleAlign = 32;
3567  SuitableAlign = 128;
3568  DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3569  SizeType = UnsignedInt;
3570  PtrDiffType = SignedInt;
3571  IntPtrType = SignedInt;
3572  RegParmMax = 3;
3573 
3574  // Use fpret for all types.
3575  RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3576  (1 << TargetInfo::Double) |
3577  (1 << TargetInfo::LongDouble));
3578 
3579  // x86-32 has atomics up to 8 bytes
3580  // FIXME: Check that we actually have cmpxchg8b before setting
3581  // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3582  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3583  }
3584  BuiltinVaListKind getBuiltinVaListKind() const override {
3586  }
3587 
3588  int getEHDataRegisterNumber(unsigned RegNo) const override {
3589  if (RegNo == 0) return 0;
3590  if (RegNo == 1) return 2;
3591  return -1;
3592  }
3593  bool validateOperandSize(StringRef Constraint,
3594  unsigned Size) const override {
3595  switch (Constraint[0]) {
3596  default: break;
3597  case 'R':
3598  case 'q':
3599  case 'Q':
3600  case 'a':
3601  case 'b':
3602  case 'c':
3603  case 'd':
3604  case 'S':
3605  case 'D':
3606  return Size <= 32;
3607  case 'A':
3608  return Size <= 64;
3609  }
3610 
3611  return X86TargetInfo::validateOperandSize(Constraint, Size);
3612  }
3613 };
3614 
3615 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3616 public:
3617  NetBSDI386TargetInfo(const llvm::Triple &Triple)
3618  : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3619 
3620  unsigned getFloatEvalMethod() const override {
3621  unsigned Major, Minor, Micro;
3622  getTriple().getOSVersion(Major, Minor, Micro);
3623  // New NetBSD uses the default rounding mode.
3624  if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3625  return X86_32TargetInfo::getFloatEvalMethod();
3626  // NetBSD before 6.99.26 defaults to "double" rounding.
3627  return 1;
3628  }
3629 };
3630 
3631 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3632 public:
3633  OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3634  : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3635  SizeType = UnsignedLong;
3636  IntPtrType = SignedLong;
3637  PtrDiffType = SignedLong;
3638  }
3639 };
3640 
3641 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3642 public:
3643  BitrigI386TargetInfo(const llvm::Triple &Triple)
3644  : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3645  SizeType = UnsignedLong;
3646  IntPtrType = SignedLong;
3647  PtrDiffType = SignedLong;
3648  }
3649 };
3650 
3651 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3652 public:
3653  DarwinI386TargetInfo(const llvm::Triple &Triple)
3654  : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3655  LongDoubleWidth = 128;
3656  LongDoubleAlign = 128;
3657  SuitableAlign = 128;
3658  MaxVectorAlign = 256;
3659  SizeType = UnsignedLong;
3660  IntPtrType = SignedLong;
3661  DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3662  HasAlignMac68kSupport = true;
3663  }
3664 
3665 };
3666 
3667 // x86-32 Windows target
3668 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3669 public:
3670  WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3671  : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3672  WCharType = UnsignedShort;
3673  DoubleAlign = LongLongAlign = 64;
3674  bool IsWinCOFF =
3675  getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3676  DescriptionString = IsWinCOFF
3677  ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
3678  : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3679  }
3680  void getTargetDefines(const LangOptions &Opts,
3681  MacroBuilder &Builder) const override {
3682  WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3683  }
3684 };
3685 
3686 // x86-32 Windows Visual Studio target
3687 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3688 public:
3689  MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3690  : WindowsX86_32TargetInfo(Triple) {
3691  LongDoubleWidth = LongDoubleAlign = 64;
3692  LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3693  }
3694  void getTargetDefines(const LangOptions &Opts,
3695  MacroBuilder &Builder) const override {
3696  WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3697  WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3698  // The value of the following reflects processor type.
3699  // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3700  // We lost the original triple, so we use the default.
3701  Builder.defineMacro("_M_IX86", "600");
3702  }
3703 };
3704 } // end anonymous namespace
3705 
3706 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3707  // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports
3708  // __declspec natively under -fms-extensions, but we define a no-op __declspec
3709  // macro anyway for pre-processor compatibility.
3710  if (Opts.MicrosoftExt)
3711  Builder.defineMacro("__declspec", "__declspec");
3712  else
3713  Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3714 
3715  if (!Opts.MicrosoftExt) {
3716  // Provide macros for all the calling convention keywords. Provide both
3717  // single and double underscore prefixed variants. These are available on
3718  // x64 as well as x86, even though they have no effect.
3719  const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3720  for (const char *CC : CCs) {
3721  std::string GCCSpelling = "__attribute__((__";
3722  GCCSpelling += CC;
3723  GCCSpelling += "__))";
3724  Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3725  Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3726  }
3727  }
3728 }
3729 
3730 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3731  Builder.defineMacro("__MSVCRT__");
3732  Builder.defineMacro("__MINGW32__");
3733  addCygMingDefines(Opts, Builder);
3734 }
3735 
3736 namespace {
3737 // x86-32 MinGW target
3738 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3739 public:
3740  MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3741  : WindowsX86_32TargetInfo(Triple) {}
3742  void getTargetDefines(const LangOptions &Opts,
3743  MacroBuilder &Builder) const override {
3744  WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3745  DefineStd(Builder, "WIN32", Opts);
3746  DefineStd(Builder, "WINNT", Opts);
3747  Builder.defineMacro("_X86_");
3748  addMinGWDefines(Opts, Builder);
3749  }
3750 };
3751 
3752 // x86-32 Cygwin target
3753 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3754 public:
3755  CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3756  : X86_32TargetInfo(Triple) {
3757  TLSSupported = false;
3758  WCharType = UnsignedShort;
3759  DoubleAlign = LongLongAlign = 64;
3760  DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3761  }
3762  void getTargetDefines(const LangOptions &Opts,
3763  MacroBuilder &Builder) const override {
3764  X86_32TargetInfo::getTargetDefines(Opts, Builder);
3765  Builder.defineMacro("_X86_");
3766  Builder.defineMacro("__CYGWIN__");
3767  Builder.defineMacro("__CYGWIN32__");
3768  addCygMingDefines(Opts, Builder);
3769  DefineStd(Builder, "unix", Opts);
3770  if (Opts.CPlusPlus)
3771  Builder.defineMacro("_GNU_SOURCE");
3772  }
3773 };
3774 
3775 // x86-32 Haiku target
3776 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3777 public:
3778  HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3779  SizeType = UnsignedLong;
3780  IntPtrType = SignedLong;
3781  PtrDiffType = SignedLong;
3782  ProcessIDType = SignedLong;
3783  this->UserLabelPrefix = "";
3784  this->TLSSupported = false;
3785  }
3786  void getTargetDefines(const LangOptions &Opts,
3787  MacroBuilder &Builder) const override {
3788  X86_32TargetInfo::getTargetDefines(Opts, Builder);
3789  Builder.defineMacro("__INTEL__");
3790  Builder.defineMacro("__HAIKU__");
3791  }
3792 };
3793 
3794 // RTEMS Target
3795 template<typename Target>
3796 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3797 protected:
3798  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3799  MacroBuilder &Builder) const override {
3800  // RTEMS defines; list based off of gcc output
3801 
3802  Builder.defineMacro("__rtems__");
3803  Builder.defineMacro("__ELF__");
3804  }
3805 
3806 public:
3807  RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3808  this->UserLabelPrefix = "";
3809 
3810  switch (Triple.getArch()) {
3811  default:
3812  case llvm::Triple::x86:
3813  // this->MCountName = ".mcount";
3814  break;
3815  case llvm::Triple::mips:
3816  case llvm::Triple::mipsel:
3817  case llvm::Triple::ppc:
3818  case llvm::Triple::ppc64:
3819  case llvm::Triple::ppc64le:
3820  // this->MCountName = "_mcount";
3821  break;
3822  case llvm::Triple::arm:
3823  // this->MCountName = "__mcount";
3824  break;
3825  }
3826  }
3827 };
3828 
3829 // x86-32 RTEMS target
3830 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3831 public:
3832  RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3833  SizeType = UnsignedLong;
3834  IntPtrType = SignedLong;
3835  PtrDiffType = SignedLong;
3836  this->UserLabelPrefix = "";
3837  }
3838  void getTargetDefines(const LangOptions &Opts,
3839  MacroBuilder &Builder) const override {
3840  X86_32TargetInfo::getTargetDefines(Opts, Builder);
3841  Builder.defineMacro("__INTEL__");
3842  Builder.defineMacro("__rtems__");
3843  }
3844 };
3845 
3846 // x86-64 generic target
3847 class X86_64TargetInfo : public X86TargetInfo {
3848 public:
3849  X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3850  const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3851  bool IsWinCOFF =
3852  getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3853  LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3854  LongDoubleWidth = 128;
3855  LongDoubleAlign = 128;
3856  LargeArrayMinWidth = 128;
3857  LargeArrayAlign = 128;
3858  SuitableAlign = 128;
3859  SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3860  PtrDiffType = IsX32 ? SignedInt : SignedLong;
3861  IntPtrType = IsX32 ? SignedInt : SignedLong;
3862  IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3863  Int64Type = IsX32 ? SignedLongLong : SignedLong;
3864  RegParmMax = 6;
3865 
3866  // Pointers are 32-bit in x32.
3867  DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3868  : IsWinCOFF
3869  ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
3870  : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3871 
3872  // Use fpret only for long double.
3873  RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3874 
3875  // Use fp2ret for _Complex long double.
3876  ComplexLongDoubleUsesFP2Ret = true;
3877 
3878  // x86-64 has atomics up to 16 bytes.
3879  MaxAtomicPromoteWidth = 128;
3880  MaxAtomicInlineWidth = 128;
3881  }
3882  BuiltinVaListKind getBuiltinVaListKind() const override {
3884  }
3885 
3886  int getEHDataRegisterNumber(unsigned RegNo) const override {
3887  if (RegNo == 0) return 0;
3888  if (RegNo == 1) return 1;
3889  return -1;
3890  }
3891 
3892  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3893  return (CC == CC_C ||
3894  CC == CC_X86VectorCall ||
3895  CC == CC_IntelOclBicc ||
3896  CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3897  }
3898 
3899  CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3900  return CC_C;
3901  }
3902 
3903  // for x32 we need it here explicitly
3904  bool hasInt128Type() const override { return true; }
3905 };
3906 
3907 // x86-64 Windows target
3908 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3909 public:
3910  WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3911  : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3912  WCharType = UnsignedShort;
3913  LongWidth = LongAlign = 32;
3914  DoubleAlign = LongLongAlign = 64;
3915  IntMaxType = SignedLongLong;
3916  Int64Type = SignedLongLong;
3917  SizeType = UnsignedLongLong;
3918  PtrDiffType = SignedLongLong;
3919  IntPtrType = SignedLongLong;
3920  this->UserLabelPrefix = "";
3921  }
3922 
3923  void getTargetDefines(const LangOptions &Opts,
3924  MacroBuilder &Builder) const override {
3925  WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3926  Builder.defineMacro("_WIN64");
3927  }
3928 
3929  BuiltinVaListKind getBuiltinVaListKind() const override {
3931  }
3932 
3933  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3934  switch (CC) {
3935  case CC_X86StdCall:
3936  case CC_X86ThisCall:
3937  case CC_X86FastCall:
3938  return CCCR_Ignore;
3939  case CC_C:
3940  case CC_X86VectorCall:
3941  case CC_IntelOclBicc:
3942  case CC_X86_64SysV:
3943  return CCCR_OK;
3944  default:
3945  return CCCR_Warning;
3946  }
3947  }
3948 };
3949 
3950 // x86-64 Windows Visual Studio target
3951 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3952 public:
3953  MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3954  : WindowsX86_64TargetInfo(Triple) {
3955  LongDoubleWidth = LongDoubleAlign = 64;
3956  LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3957  }
3958  void getTargetDefines(const LangOptions &Opts,
3959  MacroBuilder &Builder) const override {
3960  WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3961  WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3962  Builder.defineMacro("_M_X64");
3963  Builder.defineMacro("_M_AMD64");
3964  }
3965 };
3966 
3967 // x86-64 MinGW target
3968 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3969 public:
3970  MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3971  : WindowsX86_64TargetInfo(Triple) {}
3972  void getTargetDefines(const LangOptions &Opts,
3973  MacroBuilder &Builder) const override {
3974  WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3975  DefineStd(Builder, "WIN64", Opts);
3976  Builder.defineMacro("__MINGW64__");
3977  addMinGWDefines(Opts, Builder);
3978 
3979  // GCC defines this macro when it is using __gxx_personality_seh0.
3980  if (!Opts.SjLjExceptions)
3981  Builder.defineMacro("__SEH__");
3982  }
3983 };
3984 
3985 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3986 public:
3987  DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3988  : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3989  Int64Type = SignedLongLong;
3990  MaxVectorAlign = 256;
3991  // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3992  llvm::Triple T = llvm::Triple(Triple);
3993  if (T.isiOS())
3994  UseSignedCharForObjCBool = false;
3995  DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3996  }
3997 };
3998 
3999 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4000 public:
4001  OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
4002  : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
4003  IntMaxType = SignedLongLong;
4004  Int64Type = SignedLongLong;
4005  }
4006 };
4007 
4008 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4009 public:
4010  BitrigX86_64TargetInfo(const llvm::Triple &Triple)
4011  : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
4012  IntMaxType = SignedLongLong;
4013  Int64Type = SignedLongLong;
4014  }
4015 };
4016 
4017 class ARMTargetInfo : public TargetInfo {
4018  // Possible FPU choices.
4019  enum FPUMode {
4020  VFP2FPU = (1 << 0),
4021  VFP3FPU = (1 << 1),
4022  VFP4FPU = (1 << 2),
4023  NeonFPU = (1 << 3),
4024  FPARMV8 = (1 << 4)
4025  };
4026 
4027  // Possible HWDiv features.
4028  enum HWDivMode {
4029  HWDivThumb = (1 << 0),
4030  HWDivARM = (1 << 1)
4031  };
4032 
4033  static bool FPUModeIsVFP(FPUMode Mode) {
4034  return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4035  }
4036 
4037  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4038  static const char * const GCCRegNames[];
4039 
4040  std::string ABI, CPU;
4041 
4042  enum {
4043  FP_Default,
4044  FP_VFP,
4045  FP_Neon
4046  } FPMath;
4047 
4048  unsigned FPU : 5;
4049 
4050  unsigned IsAAPCS : 1;
4051  unsigned IsThumb : 1;
4052  unsigned HWDiv : 2;
4053 
4054  // Initialized via features.
4055  unsigned SoftFloat : 1;
4056  unsigned SoftFloatABI : 1;
4057 
4058  unsigned CRC : 1;
4059  unsigned Crypto : 1;
4060 
4061  // ACLE 6.5.1 Hardware floating point
4062  enum {
4063  HW_FP_HP = (1 << 1), /// half (16-bit)
4064  HW_FP_SP = (1 << 2), /// single (32-bit)
4065  HW_FP_DP = (1 << 3), /// double (64-bit)
4066  };
4067  uint32_t HW_FP;
4068 
4069  static const Builtin::Info BuiltinInfo[];
4070 
4071  static bool shouldUseInlineAtomic(const llvm::Triple &T) {
4072  StringRef ArchName = T.getArchName();
4073  if (T.getArch() == llvm::Triple::arm ||
4074  T.getArch() == llvm::Triple::armeb) {
4075  StringRef VersionStr;
4076  if (ArchName.startswith("armv"))
4077  VersionStr = ArchName.substr(4, 1);
4078  else if (ArchName.startswith("armebv"))
4079  VersionStr = ArchName.substr(6, 1);
4080  else
4081  return false;
4082  unsigned Version;
4083  if (VersionStr.getAsInteger(10, Version))
4084  return false;
4085  return Version >= 6;
4086  }
4087  assert(T.getArch() == llvm::Triple::thumb ||
4088  T.getArch() == llvm::Triple::thumbeb);
4089  StringRef VersionStr;
4090  if (ArchName.startswith("thumbv"))
4091  VersionStr = ArchName.substr(6, 1);
4092  else if (ArchName.startswith("thumbebv"))
4093  VersionStr = ArchName.substr(8, 1);
4094  else
4095  return false;
4096  unsigned Version;
4097  if (VersionStr.getAsInteger(10, Version))
4098  return false;
4099  return Version >= 7;
4100  }
4101 
4102  void setABIAAPCS() {
4103  IsAAPCS = true;
4104 
4105  DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4106  const llvm::Triple &T = getTriple();
4107 
4108  // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
4109  if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4110  T.getOS() == llvm::Triple::Bitrig)
4111  SizeType = UnsignedLong;
4112  else
4113  SizeType = UnsignedInt;
4114 
4115  switch (T.getOS()) {
4116  case llvm::Triple::NetBSD:
4117  WCharType = SignedInt;
4118  break;
4119  case llvm::Triple::Win32:
4120  WCharType = UnsignedShort;
4121  break;
4122  case llvm::Triple::Linux:
4123  default:
4124  // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4125  WCharType = UnsignedInt;
4126  break;
4127  }
4128 
4129  UseBitFieldTypeAlignment = true;
4130 
4131  ZeroLengthBitfieldBoundary = 0;
4132 
4133  // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4134  // so set preferred for small types to 32.
4135  if (T.isOSBinFormatMachO()) {
4136  DescriptionString =
4137  BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4138  : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4139  } else if (T.isOSWindows()) {
4140  assert(!BigEndian && "Windows on ARM does not support big endian");
4141  DescriptionString = "e"
4142  "-m:w"
4143  "-p:32:32"
4144  "-i64:64"
4145  "-v128:64:128"
4146  "-a:0:32"
4147  "-n32"
4148  "-S64";
4149  } else if (T.isOSNaCl()) {
4150  assert(!BigEndian && "NaCl on ARM does not support big endian");
4151  DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
4152  } else {
4153  DescriptionString =
4154  BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4155  : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4156  }
4157 
4158  // FIXME: Enumerated types are variable width in straight AAPCS.
4159  }
4160 
4161  void setABIAPCS() {
4162  const llvm::Triple &T = getTriple();
4163 
4164  IsAAPCS = false;
4165 
4166  DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4167 
4168  // size_t is unsigned int on FreeBSD.
4169  if (T.getOS() == llvm::Triple::FreeBSD)
4170  SizeType = UnsignedInt;
4171  else
4172  SizeType = UnsignedLong;
4173 
4174  // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4175  WCharType = SignedInt;
4176 
4177  // Do not respect the alignment of bit-field types when laying out
4178  // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4179  UseBitFieldTypeAlignment = false;
4180 
4181  /// gcc forces the alignment to 4 bytes, regardless of the type of the
4182  /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4183  /// gcc.
4184  ZeroLengthBitfieldBoundary = 32;
4185 
4186  if (T.isOSBinFormatMachO())
4187  DescriptionString =
4188  BigEndian
4189  ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4190  : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4191  else
4192  DescriptionString =
4193  BigEndian
4194  ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4195  : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4196 
4197  // FIXME: Override "preferred align" for double and long long.
4198  }
4199 
4200 public:
4201  ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
4202  : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
4203  IsAAPCS(true), HW_FP(0) {
4204  BigEndian = IsBigEndian;
4205 
4206  switch (getTriple().getOS()) {
4207  case llvm::Triple::NetBSD:
4208  PtrDiffType = SignedLong;
4209  break;
4210  default:
4211  PtrDiffType = SignedInt;
4212  break;
4213  }
4214 
4215  // {} in inline assembly are neon specifiers, not assembly variant
4216  // specifiers.
4217  NoAsmVariants = true;
4218 
4219  // FIXME: Should we just treat this as a feature?
4220  IsThumb = getTriple().getArchName().startswith("thumb");
4221 
4222  // FIXME: This duplicates code from the driver that sets the -target-abi
4223  // option - this code is used if -target-abi isn't passed and should
4224  // be unified in some way.
4225  if (Triple.isOSBinFormatMachO()) {
4226  // The backend is hardwired to assume AAPCS for M-class processors, ensure
4227  // the frontend matches that.
4228  if (Triple.getEnvironment() == llvm::Triple::EABI ||
4229  Triple.getOS() == llvm::Triple::UnknownOS ||
4230  StringRef(CPU).startswith("cortex-m")) {
4231  setABI("aapcs");
4232  } else {
4233  setABI("apcs-gnu");
4234  }
4235  } else if (Triple.isOSWindows()) {
4236  // FIXME: this is invalid for WindowsCE
4237  setABI("aapcs");
4238  } else {
4239  // Select the default based on the platform.
4240  switch (Triple.getEnvironment()) {
4241  case llvm::Triple::Android:
4242  case llvm::Triple::GNUEABI:
4243  case llvm::Triple::GNUEABIHF:
4244  setABI("aapcs-linux");
4245  break;
4246  case llvm::Triple::EABIHF:
4247  case llvm::Triple::EABI:
4248  setABI("aapcs");
4249  break;
4250  case llvm::Triple::GNU:
4251  setABI("apcs-gnu");
4252  break;
4253  default:
4254  if (Triple.getOS() == llvm::Triple::NetBSD)
4255  setABI("apcs-gnu");
4256  else
4257  setABI("aapcs");
4258  break;
4259  }
4260  }
4261 
4262  // ARM targets default to using the ARM C++ ABI.
4263  TheCXXABI.set(TargetCXXABI::GenericARM);
4264 
4265  // ARM has atomics up to 8 bytes
4266  MaxAtomicPromoteWidth = 64;
4267  if (shouldUseInlineAtomic(getTriple()))
4268  MaxAtomicInlineWidth = 64;
4269 
4270  // Do force alignment of members that follow zero length bitfields. If
4271  // the alignment of the zero-length bitfield is greater than the member
4272  // that follows it, `bar', `bar' will be aligned as the type of the
4273  // zero length bitfield.
4274  UseZeroLengthBitfieldAlignment = true;
4275  }
4276 
4277  StringRef getABI() const override { return ABI; }
4278 
4279  bool setABI(const std::string &Name) override {
4280  ABI = Name;
4281 
4282  // The defaults (above) are for AAPCS, check if we need to change them.
4283  //
4284  // FIXME: We need support for -meabi... we could just mangle it into the
4285  // name.
4286  if (Name == "apcs-gnu") {
4287  setABIAPCS();
4288  return true;
4289  }
4290  if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4291  setABIAAPCS();
4292  return true;
4293  }
4294  return false;
4295  }
4296 
4297  // FIXME: This should be based on Arch attributes, not CPU names.
4298  void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
4299  StringRef ArchName = getTriple().getArchName();
4300  unsigned ArchKind = llvm::ARMTargetParser::parseArch(ArchName);
4301  bool IsV8 = (ArchKind == llvm::ARM::AK_ARMV8A ||
4302  ArchKind == llvm::ARM::AK_ARMV8_1A);
4303 
4304  if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
4305  Features["vfp2"] = true;
4306  else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
4307  Features["vfp3"] = true;
4308  Features["neon"] = true;
4309  }
4310  else if (CPU == "cortex-a5") {
4311  Features["vfp4"] = true;
4312  Features["neon"] = true;
4313  } else if (CPU == "swift" || CPU == "cortex-a7" ||
4314  CPU == "cortex-a12" || CPU == "cortex-a15" ||
4315  CPU == "cortex-a17" || CPU == "krait") {
4316  Features["vfp4"] = true;
4317  Features["neon"] = true;
4318  Features["hwdiv"] = true;
4319  Features["hwdiv-arm"] = true;
4320  } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" ||
4321  CPU == "cortex-a72") {
4322  Features["fp-armv8"] = true;
4323  Features["neon"] = true;
4324  Features["hwdiv"] = true;
4325  Features["hwdiv-arm"] = true;
4326  Features["crc"] = true;
4327  Features["crypto"] = true;
4328  } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || IsV8) {
4329  Features["hwdiv"] = true;
4330  Features["hwdiv-arm"] = true;
4331  } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
4332  CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") {
4333  Features["hwdiv"] = true;
4334  }
4335  }
4336 
4337  bool handleTargetFeatures(std::vector<std::string> &Features,
4338  DiagnosticsEngine &Diags) override {
4339  FPU = 0;
4340  CRC = 0;
4341  Crypto = 0;
4342  SoftFloat = SoftFloatABI = false;
4343  HWDiv = 0;
4344 
4345  // This does not diagnose illegal cases like having both
4346  // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
4347  uint32_t HW_FP_remove = 0;
4348  for (const auto &Feature : Features) {
4349  if (Feature == "+soft-float") {
4350  SoftFloat = true;
4351  } else if (Feature == "+soft-float-abi") {
4352  SoftFloatABI = true;
4353  } else if (Feature == "+vfp2") {
4354  FPU |= VFP2FPU;
4355  HW_FP |= HW_FP_SP | HW_FP_DP;
4356  } else if (Feature == "+vfp3") {
4357  FPU |= VFP3FPU;
4358  HW_FP |= HW_FP_SP | HW_FP_DP;
4359  } else if (Feature == "+vfp4") {
4360  FPU |= VFP4FPU;
4361  HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4362  } else if (Feature == "+fp-armv8") {
4363  FPU |= FPARMV8;
4364  HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4365  } else if (Feature == "+neon") {
4366  FPU |= NeonFPU;
4367  HW_FP |= HW_FP_SP | HW_FP_DP;
4368  } else if (Feature == "+hwdiv") {
4369  HWDiv |= HWDivThumb;
4370  } else if (Feature == "+hwdiv-arm") {
4371  HWDiv |= HWDivARM;
4372  } else if (Feature == "+crc") {
4373  CRC = 1;
4374  } else if (Feature == "+crypto") {
4375  Crypto = 1;
4376  } else if (Feature == "+fp-only-sp") {
4377  HW_FP_remove |= HW_FP_DP | HW_FP_HP;
4378  }
4379  }
4380  HW_FP &= ~HW_FP_remove;
4381 
4382  if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4383  Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4384  return false;
4385  }
4386 
4387  if (FPMath == FP_Neon)
4388  Features.push_back("+neonfp");
4389  else if (FPMath == FP_VFP)
4390  Features.push_back("-neonfp");
4391 
4392  // Remove front-end specific options which the backend handles differently.
4393  auto Feature =
4394  std::find(Features.begin(), Features.end(), "+soft-float-abi");
4395  if (Feature != Features.end())
4396  Features.erase(Feature);
4397 
4398  return true;
4399  }
4400 
4401  bool hasFeature(StringRef Feature) const override {
4402  return llvm::StringSwitch<bool>(Feature)
4403  .Case("arm", true)
4404  .Case("softfloat", SoftFloat)
4405  .Case("thumb", IsThumb)
4406  .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4407  .Case("hwdiv", HWDiv & HWDivThumb)
4408  .Case("hwdiv-arm", HWDiv & HWDivARM)
4409  .Default(false);
4410  }
4411  const char *getCPUDefineSuffix(StringRef Name) const {
4412  if(Name == "generic") {
4413  auto subarch = getTriple().getSubArch();
4414  switch (subarch) {
4415  case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
4416  return "8_1A";
4417  default:
4418  break;
4419  }
4420  }
4421 
4422  unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name);
4423  if (ArchKind == llvm::ARM::AK_INVALID)
4424  return "";
4425 
4426  // For most sub-arches, the build attribute CPU name is enough.
4427  // For Cortex variants, it's slightly different.
4428  switch(ArchKind) {
4429  default:
4430  return llvm::ARMTargetParser::getCPUAttr(ArchKind);
4431  case llvm::ARM::AK_ARMV6M:
4432  case llvm::ARM::AK_ARMV6SM:
4433  return "6M";
4434  case llvm::ARM::AK_ARMV7:
4435  case llvm::ARM::AK_ARMV7A:
4436  case llvm::ARM::AK_ARMV7S:
4437  return "7A";
4438  case llvm::ARM::AK_ARMV7R:
4439  return "7R";
4440  case llvm::ARM::AK_ARMV7M:
4441  return "7M";
4442  case llvm::ARM::AK_ARMV7EM:
4443  return "7EM";
4444  case llvm::ARM::AK_ARMV8A:
4445  return "8A";
4446  case llvm::ARM::AK_ARMV8_1A:
4447  return "8_1A";
4448  }
4449  }
4450  const char *getCPUProfile(StringRef Name) const {
4451  if(Name == "generic") {
4452  auto subarch = getTriple().getSubArch();
4453  switch (subarch) {
4454  case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
4455  return "A";
4456  default:
4457  break;
4458  }
4459  }
4460 
4461  unsigned CPUArch = llvm::ARMTargetParser::parseCPUArch(Name);
4462  if (CPUArch == llvm::ARM::AK_INVALID)
4463  return "";
4464 
4465  StringRef ArchName = llvm::ARMTargetParser::getArchName(CPUArch);
4466  switch(llvm::ARMTargetParser::parseArchProfile(ArchName)) {
4467  case llvm::ARM::PK_A:
4468  return "A";
4469  case llvm::ARM::PK_R:
4470  return "R";
4471  case llvm::ARM::PK_M:
4472  return "M";
4473  default:
4474  return "";
4475  }
4476  }
4477  bool setCPU(const std::string &Name) override {
4478  if (!getCPUDefineSuffix(Name))
4479  return false;
4480 
4481  // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4482  StringRef Profile = getCPUProfile(Name);
4483  if (Profile == "M" && MaxAtomicInlineWidth) {
4484  MaxAtomicPromoteWidth = 32;
4485  MaxAtomicInlineWidth = 32;
4486  }
4487 
4488  CPU = Name;
4489  return true;
4490  }
4491  bool setFPMath(StringRef Name) override;
4492  bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4493  unsigned CPUArchVer) const {
4494  return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4495  (CPUArch.find('M') != StringRef::npos);
4496  }
4497  bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4498  unsigned CPUArchVer) const {
4499  // We check both CPUArchVer and ArchName because when only triple is
4500  // specified, the default CPU is arm1136j-s.
4501  return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4502  ArchName.endswith("v8.1a") ||
4503  ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4504  }
4505  void getTargetDefines(const LangOptions &Opts,
4506  MacroBuilder &Builder) const override {
4507  // Target identification.
4508  Builder.defineMacro("__arm");
4509  Builder.defineMacro("__arm__");
4510 
4511  // Target properties.
4512  Builder.defineMacro("__REGISTER_PREFIX__", "");
4513 
4514  StringRef CPUArch = getCPUDefineSuffix(CPU);
4515  unsigned int CPUArchVer;
4516  if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4517  llvm_unreachable("Invalid char for architecture version number");
4518  Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4519 
4520  // ACLE 6.4.1 ARM/Thumb instruction set architecture
4521  StringRef CPUProfile = getCPUProfile(CPU);
4522  StringRef ArchName = getTriple().getArchName();
4523 
4524  // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4525  Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4526  if (CPUArch[0] >= '8') {
4527  Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4528  Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4529  }
4530 
4531  // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4532  // is not defined for the M-profile.
4533  // NOTE that the deffault profile is assumed to be 'A'
4534  if (CPUProfile.empty() || CPUProfile != "M")
4535  Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4536 
4537  // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4538  // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4539  // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4540  if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4541  Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4542  else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4543  Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4544 
4545  // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4546  // instruction set such as ARM or Thumb.
4547  Builder.defineMacro("__ARM_32BIT_STATE", "1");
4548 
4549  // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4550 
4551  // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4552  if (!CPUProfile.empty())
4553  Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4554 
4555  // ACLE 6.5.1 Hardware Floating Point
4556  if (HW_FP)
4557  Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4558 
4559  // ACLE predefines.
4560  Builder.defineMacro("__ARM_ACLE", "200");
4561 
4562  // Subtarget options.
4563 
4564  // FIXME: It's more complicated than this and we don't really support
4565  // interworking.
4566  // Windows on ARM does not "support" interworking
4567  if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4568  Builder.defineMacro("__THUMB_INTERWORK__");
4569 
4570  if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4571  // Embedded targets on Darwin follow AAPCS, but not EABI.
4572  // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4573  if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4574  Builder.defineMacro("__ARM_EABI__");
4575  Builder.defineMacro("__ARM_PCS", "1");
4576 
4577  if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4578  Builder.defineMacro("__ARM_PCS_VFP", "1");
4579  }
4580 
4581  if (SoftFloat)
4582  Builder.defineMacro("__SOFTFP__");
4583 
4584  if (CPU == "xscale")
4585  Builder.defineMacro("__XSCALE__");
4586 
4587  if (IsThumb) {
4588  Builder.defineMacro("__THUMBEL__");
4589  Builder.defineMacro("__thumb__");
4590  if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4591  Builder.defineMacro("__thumb2__");
4592  }
4593  if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4594  Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4595 
4596  // Note, this is always on in gcc, even though it doesn't make sense.
4597  Builder.defineMacro("__APCS_32__");
4598 
4599  if (FPUModeIsVFP((FPUMode) FPU)) {
4600  Builder.defineMacro("__VFP_FP__");
4601  if (FPU & VFP2FPU)
4602  Builder.defineMacro("__ARM_VFPV2__");
4603  if (FPU & VFP3FPU)
4604  Builder.defineMacro("__ARM_VFPV3__");
4605  if (FPU & VFP4FPU)
4606  Builder.defineMacro("__ARM_VFPV4__");
4607  }
4608 
4609  // This only gets set when Neon instructions are actually available, unlike
4610  // the VFP define, hence the soft float and arch check. This is subtly
4611  // different from gcc, we follow the intent which was that it should be set
4612  // when Neon instructions are actually available.
4613  if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4614  Builder.defineMacro("__ARM_NEON");
4615  Builder.defineMacro("__ARM_NEON__");
4616  }
4617 
4618  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4619  Opts.ShortWChar ? "2" : "4");
4620 
4621  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4622  Opts.ShortEnums ? "1" : "4");
4623 
4624  if (CRC)
4625  Builder.defineMacro("__ARM_FEATURE_CRC32");
4626 
4627  if (Crypto)
4628  Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4629 
4630  if (CPUArchVer >= 6 && CPUArch != "6M") {
4631  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4632  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4633  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4634  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4635  }
4636 
4637  bool is5EOrAbove = (CPUArchVer >= 6 ||
4638  (CPUArchVer == 5 &&
4639  CPUArch.find('E') != StringRef::npos));
4640  bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4641  if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM"))
4642  Builder.defineMacro("__ARM_FEATURE_DSP");
4643  }
4644  void getTargetBuiltins(const Builtin::Info *&Records,
4645  unsigned &NumRecords) const override {
4646  Records = BuiltinInfo;
4648  }
4649  bool isCLZForZeroUndef() const override { return false; }
4650  BuiltinVaListKind getBuiltinVaListKind() const override {
4651  return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4652  }
4653  void getGCCRegNames(const char * const *&Names,
4654  unsigned &NumNames) const override;
4655  void getGCCRegAliases(const GCCRegAlias *&Aliases,
4656  unsigned &NumAliases) const override;
4657  bool validateAsmConstraint(const char *&Name,
4658  TargetInfo::ConstraintInfo &Info) const override {
4659  switch (*Name) {
4660  default: break;
4661  case 'l': // r0-r7
4662  case 'h': // r8-r15
4663  case 'w': // VFP Floating point register single precision
4664  case 'P': // VFP Floating point register double precision
4665  Info.setAllowsRegister();
4666  return true;
4667  case 'I':
4668  case 'J':
4669  case 'K':
4670  case 'L':
4671  case 'M':
4672  // FIXME
4673  return true;
4674  case 'Q': // A memory address that is a single base register.
4675  Info.setAllowsMemory();
4676  return true;
4677  case 'U': // a memory reference...
4678  switch (Name[1]) {
4679  case 'q': // ...ARMV4 ldrsb
4680  case 'v': // ...VFP load/store (reg+constant offset)
4681  case 'y': // ...iWMMXt load/store
4682  case 't': // address valid for load/store opaque types wider
4683  // than 128-bits
4684  case 'n': // valid address for Neon doubleword vector load/store
4685  case 'm': // valid address for Neon element and structure load/store
4686  case 's': // valid address for non-offset loads/stores of quad-word
4687  // values in four ARM registers
4688  Info.setAllowsMemory();
4689  Name++;
4690  return true;
4691  }
4692  }
4693  return false;
4694  }
4695  std::string convertConstraint(const char *&Constraint) const override {
4696  std::string R;
4697  switch (*Constraint) {
4698  case 'U': // Two-character constraint; add "^" hint for later parsing.
4699  R = std::string("^") + std::string(Constraint, 2);
4700  Constraint++;
4701  break;
4702  case 'p': // 'p' should be translated to 'r' by default.
4703  R = std::string("r");
4704  break;
4705  default:
4706  return std::string(1, *Constraint);
4707  }
4708  return R;
4709  }
4710  bool
4711  validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4712  std::string &SuggestedModifier) const override {
4713  bool isOutput = (Constraint[0] == '=');
4714  bool isInOut = (Constraint[0] == '+');
4715 
4716  // Strip off constraint modifiers.
4717  while (Constraint[0] == '=' ||
4718  Constraint[0] == '+' ||
4719  Constraint[0] == '&')
4720  Constraint = Constraint.substr(1);
4721 
4722  switch (Constraint[0]) {
4723  default: break;
4724  case 'r': {
4725  switch (Modifier) {
4726  default:
4727  return (isInOut || isOutput || Size <= 64);
4728  case 'q':
4729  // A register of size 32 cannot fit a vector type.
4730  return false;
4731  }
4732  }
4733  }
4734 
4735  return true;
4736  }
4737  const char *getClobbers() const override {
4738  // FIXME: Is this really right?
4739  return "";
4740  }
4741 
4742  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4743  return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4744  }
4745 
4746  int getEHDataRegisterNumber(unsigned RegNo) const override {
4747  if (RegNo == 0) return 0;
4748  if (RegNo == 1) return 1;
4749  return -1;
4750  }
4751 };
4752 
4753 bool ARMTargetInfo::setFPMath(StringRef Name) {
4754  if (Name == "neon") {
4755  FPMath = FP_Neon;
4756  return true;
4757  } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4758  Name == "vfp4") {
4759  FPMath = FP_VFP;
4760  return true;
4761  }
4762  return false;
4763 }
4764 
4765 const char * const ARMTargetInfo::GCCRegNames[] = {
4766  // Integer registers
4767  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4768  "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4769 
4770  // Float registers
4771  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4772  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4773  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4774  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4775 
4776  // Double registers
4777  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4778  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4779  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4780  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4781 
4782  // Quad registers
4783  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4784  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4785 };
4786 
4787 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4788  unsigned &NumNames) const {
4789  Names = GCCRegNames;
4790  NumNames = llvm::array_lengthof(GCCRegNames);
4791 }
4792 
4793 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4794  { { "a1" }, "r0" },
4795  { { "a2" }, "r1" },
4796  { { "a3" }, "r2" },
4797  { { "a4" }, "r3" },
4798  { { "v1" }, "r4" },
4799  { { "v2" }, "r5" },
4800  { { "v3" }, "r6" },
4801  { { "v4" }, "r7" },
4802  { { "v5" }, "r8" },
4803  { { "v6", "rfp" }, "r9" },
4804  { { "sl" }, "r10" },
4805  { { "fp" }, "r11" },
4806  { { "ip" }, "r12" },
4807  { { "r13" }, "sp" },
4808  { { "r14" }, "lr" },
4809  { { "r15" }, "pc" },
4810  // The S, D and Q registers overlap, but aren't really aliases; we
4811  // don't want to substitute one of these for a different-sized one.
4812 };
4813 
4814 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4815  unsigned &NumAliases) const {
4816  Aliases = GCCRegAliases;
4817  NumAliases = llvm::array_lengthof(GCCRegAliases);
4818 }
4819 
4821 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4822 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4823  ALL_LANGUAGES },
4824 #include "clang/Basic/BuiltinsNEON.def"
4825 
4826 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4827 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4828 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4829  ALL_LANGUAGES },
4830 #include "clang/Basic/BuiltinsARM.def"
4831 };
4832 
4833 class ARMleTargetInfo : public ARMTargetInfo {
4834 public:
4835  ARMleTargetInfo(const llvm::Triple &Triple)
4836  : ARMTargetInfo(Triple, false) { }
4837  void getTargetDefines(const LangOptions &Opts,
4838  MacroBuilder &Builder) const override {
4839  Builder.defineMacro("__ARMEL__");
4840  ARMTargetInfo::getTargetDefines(Opts, Builder);
4841  }
4842 };
4843 
4844 class ARMbeTargetInfo : public ARMTargetInfo {
4845 public:
4846  ARMbeTargetInfo(const llvm::Triple &Triple)
4847  : ARMTargetInfo(Triple, true) { }
4848  void getTargetDefines(const LangOptions &Opts,
4849  MacroBuilder &Builder) const override {
4850  Builder.defineMacro("__ARMEB__");
4851  Builder.defineMacro("__ARM_BIG_ENDIAN");
4852  ARMTargetInfo::getTargetDefines(Opts, Builder);
4853  }
4854 };
4855 
4856 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4857  const llvm::Triple Triple;
4858 public:
4859  WindowsARMTargetInfo(const llvm::Triple &Triple)
4860  : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4861  TLSSupported = false;
4862  WCharType = UnsignedShort;
4863  SizeType = UnsignedInt;
4864  UserLabelPrefix = "";
4865  }
4866  void getVisualStudioDefines(const LangOptions &Opts,
4867  MacroBuilder &Builder) const {
4868  WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4869 
4870  // FIXME: this is invalid for WindowsCE
4871  Builder.defineMacro("_M_ARM_NT", "1");
4872  Builder.defineMacro("_M_ARMT", "_M_ARM");
4873  Builder.defineMacro("_M_THUMB", "_M_ARM");
4874 
4875  assert((Triple.getArch() == llvm::Triple::arm ||
4876  Triple.getArch() == llvm::Triple::thumb) &&
4877  "invalid architecture for Windows ARM target info");
4878  unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4879  Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4880 
4881  // TODO map the complete set of values
4882  // 31: VFPv3 40: VFPv4
4883  Builder.defineMacro("_M_ARM_FP", "31");
4884  }
4885  BuiltinVaListKind getBuiltinVaListKind() const override {
4887  }
4888 };
4889 
4890 // Windows ARM + Itanium C++ ABI Target
4891 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4892 public:
4893  ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4894  : WindowsARMTargetInfo(Triple) {
4895  TheCXXABI.set(TargetCXXABI::GenericARM);
4896  }
4897 
4898  void getTargetDefines(const LangOptions &Opts,
4899  MacroBuilder &Builder) const override {
4900  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4901 
4902  if (Opts.MSVCCompat)
4903  WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4904  }
4905 };
4906 
4907 // Windows ARM, MS (C++) ABI
4908 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4909 public:
4910  MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4911  : WindowsARMTargetInfo(Triple) {
4912  TheCXXABI.set(TargetCXXABI::Microsoft);
4913  }
4914 
4915  void getTargetDefines(const LangOptions &Opts,
4916  MacroBuilder &Builder) const override {
4917  WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4918  WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4919  }
4920 };
4921 
4922 class DarwinARMTargetInfo :
4923  public DarwinTargetInfo<ARMleTargetInfo> {
4924 protected:
4925  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4926  MacroBuilder &Builder) const override {
4927  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4928  }
4929 
4930 public:
4931  DarwinARMTargetInfo(const llvm::Triple &Triple)
4932  : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4933  HasAlignMac68kSupport = true;
4934  // iOS always has 64-bit atomic instructions.
4935  // FIXME: This should be based off of the target features in
4936  // ARMleTargetInfo.
4937  MaxAtomicInlineWidth = 64;
4938 
4939  // Darwin on iOS uses a variant of the ARM C++ ABI.
4940  TheCXXABI.set(TargetCXXABI::iOS);
4941  }
4942 };
4943 
4944 class AArch64TargetInfo : public TargetInfo {
4945  virtual void setDescriptionString() = 0;
4946  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4947  static const char *const GCCRegNames[];
4948 
4949  enum FPUModeEnum {
4950  FPUMode,
4951  NeonMode
4952  };
4953 
4954  unsigned FPU;
4955  unsigned CRC;
4956  unsigned Crypto;
4957 
4958  static const Builtin::Info BuiltinInfo[];
4959 
4960  std::string ABI;
4961 
4962 public:
4963  AArch64TargetInfo(const llvm::Triple &Triple)
4964  : TargetInfo(Triple), ABI("aapcs") {
4965 
4966  if (getTriple().getOS() == llvm::Triple::NetBSD) {
4967  WCharType = SignedInt;
4968 
4969  // NetBSD apparently prefers consistency across ARM targets to consistency
4970  // across 64-bit targets.
4971  Int64Type = SignedLongLong;
4972  IntMaxType = SignedLongLong;
4973  } else {
4974  WCharType = UnsignedInt;
4975  Int64Type = SignedLong;
4976  IntMaxType = SignedLong;
4977  }
4978 
4979  LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4980  MaxVectorAlign = 128;
4981  MaxAtomicInlineWidth = 128;
4982  MaxAtomicPromoteWidth = 128;
4983 
4984  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
4985  LongDoubleFormat = &llvm::APFloat::IEEEquad;
4986 
4987  // {} in inline assembly are neon specifiers, not assembly variant
4988  // specifiers.
4989  NoAsmVariants = true;
4990 
4991  // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
4992  // contributes to the alignment of the containing aggregate in the same way
4993  // a plain (non bit-field) member of that type would, without exception for
4994  // zero-sized or anonymous bit-fields."
4995  UseBitFieldTypeAlignment = true;
4996  UseZeroLengthBitfieldAlignment = true;
4997 
4998  // AArch64 targets default to using the ARM C++ ABI.
4999  TheCXXABI.set(TargetCXXABI::GenericAArch64);
5000  }
5001 
5002  StringRef getABI() const override { return ABI; }
5003  bool setABI(const std::string &Name) override {
5004  if (Name != "aapcs" && Name != "darwinpcs")
5005  return false;
5006 
5007  ABI = Name;
5008  return true;
5009  }
5010 
5011  bool setCPU(const std::string &Name) override {
5012  bool CPUKnown = llvm::StringSwitch<bool>(Name)
5013  .Case("generic", true)
5014  .Cases("cortex-a53", "cortex-a57", "cortex-a72", true)
5015  .Case("cyclone", true)
5016  .Default(false);
5017  return CPUKnown;
5018  }
5019 
5020  void getTargetDefines(const LangOptions &Opts,
5021  MacroBuilder &Builder) const override {
5022  // Target identification.
5023  Builder.defineMacro("__aarch64__");
5024 
5025  // Target properties.
5026  Builder.defineMacro("_LP64");
5027  Builder.defineMacro("__LP64__");
5028 
5029  // ACLE predefines. Many can only have one possible value on v8 AArch64.
5030  Builder.defineMacro("__ARM_ACLE", "200");
5031  Builder.defineMacro("__ARM_ARCH", "8");
5032  Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
5033 
5034  Builder.defineMacro("__ARM_64BIT_STATE");
5035  Builder.defineMacro("__ARM_PCS_AAPCS64");
5036  Builder.defineMacro("__ARM_ARCH_ISA_A64");
5037 
5038  Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
5039  Builder.defineMacro("__ARM_FEATURE_CLZ");
5040  Builder.defineMacro("__ARM_FEATURE_FMA");
5041  Builder.defineMacro("__ARM_FEATURE_DIV");
5042  Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
5043  Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
5044  Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
5045  Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
5046 
5047  Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
5048 
5049  // 0xe implies support for half, single and double precision operations.
5050  Builder.defineMacro("__ARM_FP", "0xe");
5051 
5052  // PCS specifies this for SysV variants, which is all we support. Other ABIs
5053  // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
5054  Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
5055 
5056  if (Opts.FastMath || Opts.FiniteMathOnly)
5057  Builder.defineMacro("__ARM_FP_FAST");
5058 
5059  if (Opts.C99 && !Opts.Freestanding)
5060  Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
5061 
5062  Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
5063 
5064  Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5065  Opts.ShortEnums ? "1" : "4");
5066 
5067  if (FPU == NeonMode) {
5068  Builder.defineMacro("__ARM_NEON");
5069  // 64-bit NEON supports half, single and double precision operations.
5070  Builder.defineMacro("__ARM_NEON_FP", "0xe");
5071  }
5072 
5073  if (CRC)
5074  Builder.defineMacro("__ARM_FEATURE_CRC32");
5075 
5076  if (Crypto)
5077  Builder.defineMacro("__ARM_FEATURE_CRYPTO");
5078 
5079  // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
5080  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5081  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5082  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5083  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5084  }
5085 
5086  void getTargetBuiltins(const Builtin::Info *&Records,
5087  unsigned &NumRecords) const override {
5088  Records = BuiltinInfo;
5090  }
5091 
5092  bool hasFeature(StringRef Feature) const override {
5093  return Feature == "aarch64" ||
5094  Feature == "arm64" ||
5095  (Feature == "neon" && FPU == NeonMode);
5096  }
5097 
5098  bool handleTargetFeatures(std::vector<std::string> &Features,
5099  DiagnosticsEngine &Diags) override {
5100  FPU = FPUMode;
5101  CRC = 0;
5102  Crypto = 0;
5103  for (unsigned i = 0, e = Features.size(); i != e; ++i) {
5104  if (Features[i] == "+neon")
5105  FPU = NeonMode;
5106  if (Features[i] == "+crc")
5107  CRC = 1;
5108  if (Features[i] == "+crypto")
5109  Crypto = 1;
5110  }
5111 
5112  setDescriptionString();
5113 
5114  return true;
5115  }
5116 
5117  bool isCLZForZeroUndef() const override { return false; }
5118 
5119  BuiltinVaListKind getBuiltinVaListKind() const override {
5121  }
5122 
5123  void getGCCRegNames(const char *const *&Names,
5124  unsigned &NumNames) const override;
5125  void getGCCRegAliases(const GCCRegAlias *&Aliases,
5126  unsigned &NumAliases) const override;
5127 
5128  bool validateAsmConstraint(const char *&Name,
5129  TargetInfo::ConstraintInfo &Info) const override {
5130  switch (*Name) {
5131  default:
5132  return false;
5133  case 'w': // Floating point and SIMD registers (V0-V31)
5134  Info.setAllowsRegister();
5135  return true;
5136  case 'I': // Constant that can be used with an ADD instruction
5137  case 'J': // Constant that can be used with a SUB instruction
5138  case 'K': // Constant that can be used with a 32-bit logical instruction
5139  case 'L': // Constant that can be used with a 64-bit logical instruction
5140  case 'M': // Constant that can be used as a 32-bit MOV immediate
5141  case 'N': // Constant that can be used as a 64-bit MOV immediate
5142  case 'Y': // Floating point constant zero
5143  case 'Z': // Integer constant zero
5144  return true;
5145  case 'Q': // A memory reference with base register and no offset
5146  Info.setAllowsMemory();
5147  return true;
5148  case 'S': // A symbolic address
5149  Info.setAllowsRegister();
5150  return true;
5151  case 'U':
5152  // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
5153  // Utf: A memory address suitable for ldp/stp in TF mode.
5154  // Usa: An absolute symbolic address.
5155  // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
5156  llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
5157  case 'z': // Zero register, wzr or xzr
5158  Info.setAllowsRegister();
5159  return true;
5160  case 'x': // Floating point and SIMD registers (V0-V15)
5161  Info.setAllowsRegister();
5162  return true;
5163  }
5164  return false;
5165  }
5166 
5167  bool
5168  validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5169  std::string &SuggestedModifier) const override {
5170  // Strip off constraint modifiers.
5171  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
5172  Constraint = Constraint.substr(1);
5173 
5174  switch (Constraint[0]) {
5175  default:
5176  return true;
5177  case 'z':
5178  case 'r': {
5179  switch (Modifier) {
5180  case 'x':
5181  case 'w':
5182  // For now assume that the person knows what they're
5183  // doing with the modifier.
5184  return true;
5185  default:
5186  // By default an 'r' constraint will be in the 'x'
5187  // registers.
5188  if (Size == 64)
5189  return true;
5190 
5191  SuggestedModifier = "w";
5192  return false;
5193  }
5194  }
5195  }
5196  }
5197 
5198  const char *getClobbers() const override { return ""; }
5199 
5200  int getEHDataRegisterNumber(unsigned RegNo) const override {
5201  if (RegNo == 0)
5202  return 0;
5203  if (RegNo == 1)
5204  return 1;
5205  return -1;
5206  }
5207 };
5208 
5209 const char *const AArch64TargetInfo::GCCRegNames[] = {
5210  // 32-bit Integer registers
5211  "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
5212  "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
5213  "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
5214 
5215  // 64-bit Integer registers
5216  "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
5217  "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
5218  "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
5219 
5220  // 32-bit floating point regsisters
5221  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
5222  "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
5223  "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5224 
5225  // 64-bit floating point regsisters
5226  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
5227  "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5228  "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5229 
5230  // Vector registers
5231  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
5232  "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5233  "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5234 };
5235 
5236 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
5237  unsigned &NumNames) const {
5238  Names = GCCRegNames;
5239  NumNames = llvm::array_lengthof(GCCRegNames);
5240 }
5241 
5242 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5243  { { "w31" }, "wsp" },
5244  { { "x29" }, "fp" },
5245  { { "x30" }, "lr" },
5246  { { "x31" }, "sp" },
5247  // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5248  // don't want to substitute one of these for a different-sized one.
5249 };
5250 
5251 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5252  unsigned &NumAliases) const {
5253  Aliases = GCCRegAliases;
5254  NumAliases = llvm::array_lengthof(GCCRegAliases);
5255 }
5256 
5258 #define BUILTIN(ID, TYPE, ATTRS) \
5259  { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5260 #include "clang/Basic/BuiltinsNEON.def"
5261 
5262 #define BUILTIN(ID, TYPE, ATTRS) \
5263  { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5264 #include "clang/Basic/BuiltinsAArch64.def"
5265 };
5266 
5267 class AArch64leTargetInfo : public AArch64TargetInfo {
5268  void setDescriptionString() override {
5269  if (getTriple().isOSBinFormatMachO())
5270  DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
5271  else
5272  DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
5273  }
5274 
5275 public:
5276  AArch64leTargetInfo(const llvm::Triple &Triple)
5277  : AArch64TargetInfo(Triple) {
5278  BigEndian = false;
5279  }
5280  void getTargetDefines(const LangOptions &Opts,
5281  MacroBuilder &Builder) const override {
5282  Builder.defineMacro("__AARCH64EL__");
5283  AArch64TargetInfo::getTargetDefines(Opts, Builder);
5284  }
5285 };
5286 
5287 class AArch64beTargetInfo : public AArch64TargetInfo {
5288  void setDescriptionString() override {
5289  assert(!getTriple().isOSBinFormatMachO());
5290  DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
5291  }
5292 
5293 public:
5294  AArch64beTargetInfo(const llvm::Triple &Triple)
5295  : AArch64TargetInfo(Triple) { }
5296  void getTargetDefines(const LangOptions &Opts,
5297  MacroBuilder &Builder) const override {
5298  Builder.defineMacro("__AARCH64EB__");
5299  Builder.defineMacro("__AARCH_BIG_ENDIAN");
5300  Builder.defineMacro("__ARM_BIG_ENDIAN");
5301  AArch64TargetInfo::getTargetDefines(Opts, Builder);
5302  }
5303 };
5304 
5305 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5306 protected:
5307  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5308  MacroBuilder &Builder) const override {
5309  Builder.defineMacro("__AARCH64_SIMD__");
5310  Builder.defineMacro("__ARM64_ARCH_8__");
5311  Builder.defineMacro("__ARM_NEON__");
5312  Builder.defineMacro("__LITTLE_ENDIAN__");
5313  Builder.defineMacro("__REGISTER_PREFIX__", "");
5314  Builder.defineMacro("__arm64", "1");
5315  Builder.defineMacro("__arm64__", "1");
5316 
5317  getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5318  }
5319 
5320 public:
5321  DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5322  : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5323  Int64Type = SignedLongLong;
5324  WCharType = SignedInt;
5325  UseSignedCharForObjCBool = false;
5326 
5327  LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5328  LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5329 
5330  TheCXXABI.set(TargetCXXABI::iOS64);
5331  }
5332 
5333  BuiltinVaListKind getBuiltinVaListKind() const override {
5335  }
5336 };
5337 
5338 // Hexagon abstract base class
5339 class HexagonTargetInfo : public TargetInfo {
5340  static const Builtin::Info BuiltinInfo[];
5341  static const char * const GCCRegNames[];
5342  static const TargetInfo::GCCRegAlias GCCRegAliases[];
5343  std::string CPU;
5344 public:
5345  HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5346  BigEndian = false;
5347  DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5348 
5349  // {} in inline assembly are packet specifiers, not assembly variant
5350  // specifiers.
5351  NoAsmVariants = true;
5352  }
5353 
5354  void getTargetBuiltins(const Builtin::Info *&Records,
5355  unsigned &NumRecords) const override {
5356  Records = BuiltinInfo;
5358  }
5359 
5360  bool validateAsmConstraint(const char *&Name,
5361  TargetInfo::ConstraintInfo &Info) const override {
5362  return true;
5363  }
5364 
5365  void getTargetDefines(const LangOptions &Opts,
5366  MacroBuilder &Builder) const override;
5367 
5368  bool hasFeature(StringRef Feature) const override {
5369  return Feature == "hexagon";
5370  }
5371 
5372  BuiltinVaListKind getBuiltinVaListKind() const override {
5374  }
5375  void getGCCRegNames(const char * const *&Names,
5376  unsigned &NumNames) const override;
5377  void getGCCRegAliases(const GCCRegAlias *&Aliases,
5378  unsigned &NumAliases) const override;
5379  const char *getClobbers() const override {
5380  return "";
5381  }
5382 
5383  static const char *getHexagonCPUSuffix(StringRef Name) {
5384  return llvm::StringSwitch<const char*>(Name)
5385  .Case("hexagonv4", "4")
5386  .Case("hexagonv5", "5")
5387  .Default(nullptr);
5388  }
5389 
5390  bool setCPU(const std::string &Name) override {
5391  if (!getHexagonCPUSuffix(Name))
5392  return false;
5393 
5394  CPU = Name;
5395  return true;
5396  }
5397 };
5398 
5399 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5400  MacroBuilder &Builder) const {
5401  Builder.defineMacro("qdsp6");
5402  Builder.defineMacro("__qdsp6", "1");
5403  Builder.defineMacro("__qdsp6__", "1");
5404 
5405  Builder.defineMacro("hexagon");
5406  Builder.defineMacro("__hexagon", "1");
5407  Builder.defineMacro("__hexagon__", "1");
5408 
5409  if(CPU == "hexagonv1") {
5410  Builder.defineMacro("__HEXAGON_V1__");
5411  Builder.defineMacro("__HEXAGON_ARCH__", "1");
5412  if(Opts.HexagonQdsp6Compat) {
5413  Builder.defineMacro("__QDSP6_V1__");
5414  Builder.defineMacro("__QDSP6_ARCH__", "1");
5415  }
5416  }
5417  else if(CPU == "hexagonv2") {
5418  Builder.defineMacro("__HEXAGON_V2__");
5419  Builder.defineMacro("__HEXAGON_ARCH__", "2");
5420  if(Opts.HexagonQdsp6Compat) {
5421  Builder.defineMacro("__QDSP6_V2__");
5422  Builder.defineMacro("__QDSP6_ARCH__", "2");
5423  }
5424  }
5425  else if(CPU == "hexagonv3") {
5426  Builder.defineMacro("__HEXAGON_V3__");
5427  Builder.defineMacro("__HEXAGON_ARCH__", "3");
5428  if(Opts.HexagonQdsp6Compat) {
5429  Builder.defineMacro("__QDSP6_V3__");
5430  Builder.defineMacro("__QDSP6_ARCH__", "3");
5431  }
5432  }
5433  else if(CPU == "hexagonv4") {
5434  Builder.defineMacro("__HEXAGON_V4__");
5435  Builder.defineMacro("__HEXAGON_ARCH__", "4");
5436  if(Opts.HexagonQdsp6Compat) {
5437  Builder.defineMacro("__QDSP6_V4__");
5438  Builder.defineMacro("__QDSP6_ARCH__", "4");
5439  }
5440  }
5441  else if(CPU == "hexagonv5") {
5442  Builder.defineMacro("__HEXAGON_V5__");
5443  Builder.defineMacro("__HEXAGON_ARCH__", "5");
5444  if(Opts.HexagonQdsp6Compat) {
5445  Builder.defineMacro("__QDSP6_V5__");
5446  Builder.defineMacro("__QDSP6_ARCH__", "5");
5447  }
5448  }
5449 }
5450 
5451 const char * const HexagonTargetInfo::GCCRegNames[] = {
5452  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5453  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5454  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5455  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5456  "p0", "p1", "p2", "p3",
5457  "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5458 };
5459 
5460 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5461  unsigned &NumNames) const {
5462  Names = GCCRegNames;
5463  NumNames = llvm::array_lengthof(GCCRegNames);
5464 }
5465 
5466 
5467 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5468  { { "sp" }, "r29" },
5469  { { "fp" }, "r30" },
5470  { { "lr" }, "r31" },
5471  };
5472 
5473 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5474  unsigned &NumAliases) const {
5475  Aliases = GCCRegAliases;
5476  NumAliases = llvm::array_lengthof(GCCRegAliases);
5477 }
5478 
5479 
5481 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5482 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5483  ALL_LANGUAGES },
5484 #include "clang/Basic/BuiltinsHexagon.def"
5485 };
5486 
5487 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5488 class SparcTargetInfo : public TargetInfo {
5489  static const TargetInfo::GCCRegAlias GCCRegAliases[];
5490  static const char * const GCCRegNames[];
5491  bool SoftFloat;
5492 public:
5493  SparcTargetInfo(const llvm::Triple &Triple)
5494  : TargetInfo(Triple), SoftFloat(false) {}
5495 
5496  bool handleTargetFeatures(std::vector<std::string> &Features,
5497  DiagnosticsEngine &Diags) override {
5498  // The backend doesn't actually handle soft float yet, but in case someone
5499  // is using the support for the front end continue to support it.
5500  auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
5501  if (Feature != Features.end()) {
5502  SoftFloat = true;
5503  Features.erase(Feature);
5504  }
5505  return true;
5506  }
5507  void getTargetDefines(const LangOptions &Opts,
5508  MacroBuilder &Builder) const override {
5509  DefineStd(Builder, "sparc", Opts);
5510  Builder.defineMacro("__REGISTER_PREFIX__", "");
5511 
5512  if (SoftFloat)
5513  Builder.defineMacro("SOFT_FLOAT", "1");
5514  }
5515 
5516  bool hasFeature(StringRef Feature) const override {
5517  return llvm::StringSwitch<bool>(Feature)
5518  .Case("softfloat", SoftFloat)
5519  .Case("sparc", true)
5520  .Default(false);
5521  }
5522 
5523  void getTargetBuiltins(const Builtin::Info *&Records,
5524  unsigned &NumRecords) const override {
5525  // FIXME: Implement!
5526  }
5527  BuiltinVaListKind getBuiltinVaListKind() const override {
5529  }
5530  void getGCCRegNames(const char * const *&Names,
5531  unsigned &NumNames) const override;
5532  void getGCCRegAliases(const GCCRegAlias *&Aliases,
5533  unsigned &NumAliases) const override;
5534  bool validateAsmConstraint(const char *&Name,
5535  TargetInfo::ConstraintInfo &info) const override {
5536  // FIXME: Implement!
5537  switch (*Name) {
5538  case 'I': // Signed 13-bit constant
5539  case 'J': // Zero
5540  case 'K': // 32-bit constant with the low 12 bits clear
5541  case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5542  case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5543  case 'N': // Same as 'K' but zext (required for SIMode)
5544  case 'O': // The constant 4096
5545  return true;
5546  }
5547  return false;
5548  }
5549  const char *getClobbers() const override {
5550  // FIXME: Implement!
5551  return "";
5552  }
5553 };
5554 
5555 const char * const SparcTargetInfo::GCCRegNames[] = {
5556  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5557  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5558  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5559  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5560 };
5561 
5562 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5563  unsigned &NumNames) const {
5564  Names = GCCRegNames;
5565  NumNames = llvm::array_lengthof(GCCRegNames);
5566 }
5567 
5568 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5569  { { "g0" }, "r0" },
5570  { { "g1" }, "r1" },
5571  { { "g2" }, "r2" },
5572  { { "g3" }, "r3" },
5573  { { "g4" }, "r4" },
5574  { { "g5" }, "r5" },
5575  { { "g6" }, "r6" },
5576  { { "g7" }, "r7" },
5577  { { "o0" }, "r8" },
5578  { { "o1" }, "r9" },
5579  { { "o2" }, "r10" },
5580  { { "o3" }, "r11" },
5581  { { "o4" }, "r12" },
5582  { { "o5" }, "r13" },
5583  { { "o6", "sp" }, "r14" },
5584  { { "o7" }, "r15" },
5585  { { "l0" }, "r16" },
5586  { { "l1" }, "r17" },
5587  { { "l2" }, "r18" },
5588  { { "l3" }, "r19" },
5589  { { "l4" }, "r20" },
5590  { { "l5" }, "r21" },
5591  { { "l6" }, "r22" },
5592  { { "l7" }, "r23" },
5593  { { "i0" }, "r24" },
5594  { { "i1" }, "r25" },
5595  { { "i2" }, "r26" },
5596  { { "i3" }, "r27" },
5597  { { "i4" }, "r28" },
5598  { { "i5" }, "r29" },
5599  { { "i6", "fp" }, "r30" },
5600  { { "i7" }, "r31" },
5601 };
5602 
5603 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5604  unsigned &NumAliases) const {
5605  Aliases = GCCRegAliases;
5606  NumAliases = llvm::array_lengthof(GCCRegAliases);
5607 }
5608 
5609 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5610 class SparcV8TargetInfo : public SparcTargetInfo {
5611 public:
5612  SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5613  DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5614  // NetBSD uses long (same as llvm default); everyone else uses int.
5615  if (getTriple().getOS() == llvm::Triple::NetBSD) {
5616  SizeType = UnsignedLong;
5617  IntPtrType = SignedLong;
5618  PtrDiffType = SignedLong;
5619  } else {
5620  SizeType = UnsignedInt;
5621  IntPtrType = SignedInt;
5622  PtrDiffType = SignedInt;
5623  }
5624  }
5625 
5626  void getTargetDefines(const LangOptions &Opts,
5627  MacroBuilder &Builder) const override {
5628  SparcTargetInfo::getTargetDefines(Opts, Builder);
5629  Builder.defineMacro("__sparcv8");
5630  }
5631 };
5632 
5633 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
5634 class SparcV8elTargetInfo : public SparcV8TargetInfo {
5635  public:
5636  SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) {
5637  DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64";
5638  BigEndian = false;
5639  }
5640 };
5641 
5642 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5643 class SparcV9TargetInfo : public SparcTargetInfo {
5644 public:
5645  SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5646  // FIXME: Support Sparc quad-precision long double?
5647  DescriptionString = "E-m:e-i64:64-n32:64-S128";
5648  // This is an LP64 platform.
5649  LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5650 
5651  // OpenBSD uses long long for int64_t and intmax_t.
5652  if (getTriple().getOS() == llvm::Triple::OpenBSD)
5653  IntMaxType = SignedLongLong;
5654  else
5655  IntMaxType = SignedLong;
5656  Int64Type = IntMaxType;
5657 
5658  // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5659  // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5660  LongDoubleWidth = 128;
5661  LongDoubleAlign = 128;
5662  LongDoubleFormat = &llvm::APFloat::IEEEquad;
5663  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5664  }
5665 
5666  void getTargetDefines(const LangOptions &Opts,
5667  MacroBuilder &Builder) const override {
5668  SparcTargetInfo::getTargetDefines(Opts, Builder);
5669  Builder.defineMacro("__sparcv9");
5670  Builder.defineMacro("__arch64__");
5671  // Solaris doesn't need these variants, but the BSDs do.
5672  if (getTriple().getOS() != llvm::Triple::Solaris) {
5673  Builder.defineMacro("__sparc64__");
5674  Builder.defineMacro("__sparc_v9__");
5675  Builder.defineMacro("__sparcv9__");
5676  }
5677  }
5678 
5679  bool setCPU(const std::string &Name) override {
5680  bool CPUKnown = llvm::StringSwitch<bool>(Name)
5681  .Case("v9", true)
5682  .Case("ultrasparc", true)
5683  .Case("ultrasparc3", true)
5684  .Case("niagara", true)
5685  .Case("niagara2", true)
5686  .Case("niagara3", true)
5687  .Case("niagara4", true)
5688  .Default(false);
5689 
5690  // No need to store the CPU yet. There aren't any CPU-specific
5691  // macros to define.
5692  return CPUKnown;
5693  }
5694 };
5695 
5696 class SystemZTargetInfo : public TargetInfo {
5697  static const Builtin::Info BuiltinInfo[];
5698  static const char *const GCCRegNames[];
5699  std::string CPU;
5700  bool HasTransactionalExecution;
5701  bool HasVector;
5702 
5703 public:
5704  SystemZTargetInfo(const llvm::Triple &Triple)
5705  : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) {
5706  IntMaxType = SignedLong;
5707  Int64Type = SignedLong;
5708  TLSSupported = true;
5709  IntWidth = IntAlign = 32;
5710  LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5711  PointerWidth = PointerAlign = 64;
5712  LongDoubleWidth = 128;
5713  LongDoubleAlign = 64;
5714  LongDoubleFormat = &llvm::APFloat::IEEEquad;
5715  DefaultAlignForAttributeAligned = 64;
5716  MinGlobalAlign = 16;
5717  DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5718  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5719  }
5720  void getTargetDefines(const LangOptions &Opts,
5721  MacroBuilder &Builder) const override {
5722  Builder.defineMacro("__s390__");
5723  Builder.defineMacro("__s390x__");
5724  Builder.defineMacro("__zarch__");
5725  Builder.defineMacro("__LONG_DOUBLE_128__");
5726  if (HasTransactionalExecution)
5727  Builder.defineMacro("__HTM__");
5728  if (Opts.ZVector)
5729  Builder.defineMacro("__VEC__", "10301");
5730  }
5731  void getTargetBuiltins(const Builtin::Info *&Records,
5732  unsigned &NumRecords) const override {
5733  Records = BuiltinInfo;
5735  }
5736 
5737  void getGCCRegNames(const char *const *&Names,
5738  unsigned &NumNames) const override;
5739  void getGCCRegAliases(const GCCRegAlias *&Aliases,
5740  unsigned &NumAliases) const override {
5741  // No aliases.
5742  Aliases = nullptr;
5743  NumAliases = 0;
5744  }
5745  bool validateAsmConstraint(const char *&Name,
5746  TargetInfo::ConstraintInfo &info) const override;
5747  const char *getClobbers() const override {
5748  // FIXME: Is this really right?
5749  return "";
5750  }
5751  BuiltinVaListKind getBuiltinVaListKind() const override {
5753  }
5754  bool setCPU(const std::string &Name) override {
5755  CPU = Name;
5756  bool CPUKnown = llvm::StringSwitch<bool>(Name)
5757  .Case("z10", true)
5758  .Case("z196", true)
5759  .Case("zEC12", true)
5760  .Case("z13", true)
5761  .Default(false);
5762 
5763  return CPUKnown;
5764  }
5765  void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5766  if (CPU == "zEC12")
5767  Features["transactional-execution"] = true;
5768  if (CPU == "z13") {
5769  Features["transactional-execution"] = true;
5770  Features["vector"] = true;
5771  }
5772  }
5773 
5774  bool handleTargetFeatures(std::vector<std::string> &Features,
5775  DiagnosticsEngine &Diags) override {
5776  HasTransactionalExecution = false;
5777  for (unsigned i = 0, e = Features.size(); i != e; ++i) {
5778  if (Features[i] == "+transactional-execution")
5779  HasTransactionalExecution = true;
5780  if (Features[i] == "+vector")
5781  HasVector = true;
5782  }
5783  // If we use the vector ABI, vector types are 64-bit aligned.
5784  if (HasVector) {
5785  MaxVectorAlign = 64;
5786  DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
5787  "-v128:64-a:8:16-n32:64";
5788  }
5789  return true;
5790  }
5791 
5792  bool hasFeature(StringRef Feature) const override {
5793  return llvm::StringSwitch<bool>(Feature)
5794  .Case("systemz", true)
5795  .Case("htm", HasTransactionalExecution)
5796  .Case("vx", HasVector)
5797  .Default(false);
5798  }
5799 
5800  StringRef getABI() const override {
5801  if (HasVector)
5802  return "vector";
5803  return "";
5804  }
5805 
5806  bool useFloat128ManglingForLongDouble() const override {
5807  return true;
5808  }
5809 };
5810 
5812 #define BUILTIN(ID, TYPE, ATTRS) \
5813  { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5814 #include "clang/Basic/BuiltinsSystemZ.def"
5815 };
5816 
5817 const char *const SystemZTargetInfo::GCCRegNames[] = {
5818  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5819  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5820  "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
5821  "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
5822 };
5823 
5824 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5825  unsigned &NumNames) const {
5826  Names = GCCRegNames;
5827  NumNames = llvm::array_lengthof(GCCRegNames);
5828 }
5829 
5830 bool SystemZTargetInfo::
5831 validateAsmConstraint(const char *&Name,
5832  TargetInfo::ConstraintInfo &Info) const {
5833  switch (*Name) {
5834  default:
5835  return false;
5836 
5837  case 'a': // Address register
5838  case 'd': // Data register (equivalent to 'r')
5839  case 'f': // Floating-point register
5840  Info.setAllowsRegister();
5841  return true;
5842 
5843  case 'I': // Unsigned 8-bit constant
5844  case 'J': // Unsigned 12-bit constant
5845  case 'K': // Signed 16-bit constant
5846  case 'L': // Signed 20-bit displacement (on all targets we support)
5847  case 'M': // 0x7fffffff
5848  return true;
5849 
5850  case 'Q': // Memory with base and unsigned 12-bit displacement
5851  case 'R': // Likewise, plus an index
5852  case 'S': // Memory with base and signed 20-bit displacement
5853  case 'T': // Likewise, plus an index
5854  Info.setAllowsMemory();
5855  return true;
5856  }
5857 }
5858 
5859  class MSP430TargetInfo : public TargetInfo {
5860  static const char * const GCCRegNames[];
5861  public:
5862  MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5863  BigEndian = false;
5864  TLSSupported = false;
5865  IntWidth = 16; IntAlign = 16;
5866  LongWidth = 32; LongLongWidth = 64;
5867  LongAlign = LongLongAlign = 16;
5868  PointerWidth = 16; PointerAlign = 16;
5869  SuitableAlign = 16;
5870  SizeType = UnsignedInt;
5871  IntMaxType = SignedLongLong;
5872  IntPtrType = SignedInt;
5873  PtrDiffType = SignedInt;
5874  SigAtomicType = SignedLong;
5875  DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5876  }
5877  void getTargetDefines(const LangOptions &Opts,
5878  MacroBuilder &Builder) const override {
5879  Builder.defineMacro("MSP430");
5880  Builder.defineMacro("__MSP430__");
5881  // FIXME: defines for different 'flavours' of MCU
5882  }
5883  void getTargetBuiltins(const Builtin::Info *&Records,
5884  unsigned &NumRecords) const override {
5885  // FIXME: Implement.
5886  Records = nullptr;
5887  NumRecords = 0;
5888  }
5889  bool hasFeature(StringRef Feature) const override {
5890  return Feature == "msp430";
5891  }
5892  void getGCCRegNames(const char * const *&Names,
5893  unsigned &NumNames) const override;
5894  void getGCCRegAliases(const GCCRegAlias *&Aliases,
5895  unsigned &NumAliases) const override {
5896  // No aliases.
5897  Aliases = nullptr;
5898  NumAliases = 0;
5899  }
5900  bool
5901  validateAsmConstraint(const char *&Name,
5902  TargetInfo::ConstraintInfo &info) const override {
5903  // FIXME: implement
5904  switch (*Name) {
5905  case 'K': // the constant 1
5906  case 'L': // constant -1^20 .. 1^19
5907  case 'M': // constant 1-4:
5908  return true;
5909  }
5910  // No target constraints for now.
5911  return false;
5912  }
5913  const char *getClobbers() const override {
5914  // FIXME: Is this really right?
5915  return "";
5916  }
5917  BuiltinVaListKind getBuiltinVaListKind() const override {
5918  // FIXME: implement
5920  }
5921  };
5922 
5923  const char * const MSP430TargetInfo::GCCRegNames[] = {
5924  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5925  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5926  };
5927 
5928  void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5929  unsigned &NumNames) const {
5930  Names = GCCRegNames;
5931  NumNames = llvm::array_lengthof(GCCRegNames);
5932  }
5933 
5934  // LLVM and Clang cannot be used directly to output native binaries for
5935  // target, but is used to compile C code to llvm bitcode with correct
5936  // type and alignment information.
5937  //
5938  // TCE uses the llvm bitcode as input and uses it for generating customized
5939  // target processor and program binary. TCE co-design environment is
5940  // publicly available in http://tce.cs.tut.fi
5941 
5942  static const unsigned TCEOpenCLAddrSpaceMap[] = {
5943  3, // opencl_global
5944  4, // opencl_local
5945  5, // opencl_constant
5946  // FIXME: generic has to be added to the target
5947  0, // opencl_generic
5948  0, // cuda_device
5949  0, // cuda_constant
5950  0 // cuda_shared
5951  };
5952 
5953  class TCETargetInfo : public TargetInfo{
5954  public:
5955  TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5956  TLSSupported = false;
5957  IntWidth = 32;
5958  LongWidth = LongLongWidth = 32;
5959  PointerWidth = 32;
5960  IntAlign = 32;
5961  LongAlign = LongLongAlign = 32;
5962  PointerAlign = 32;
5963  SuitableAlign = 32;
5964  SizeType = UnsignedInt;
5965  IntMaxType = SignedLong;
5966  IntPtrType = SignedInt;
5967  PtrDiffType = SignedInt;
5968  FloatWidth = 32;
5969  FloatAlign = 32;
5970  DoubleWidth = 32;
5971  DoubleAlign = 32;
5972  LongDoubleWidth = 32;
5973  LongDoubleAlign = 32;
5974  FloatFormat = &llvm::APFloat::IEEEsingle;
5975  DoubleFormat = &llvm::APFloat::IEEEsingle;
5976  LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5977  DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5978  "-f64:32-v64:32-v128:32-a:0:32-n32";
5979  AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5980  UseAddrSpaceMapMangling = true;
5981  }
5982 
5983  void getTargetDefines(const LangOptions &Opts,
5984  MacroBuilder &Builder) const override {
5985  DefineStd(Builder, "tce", Opts);
5986  Builder.defineMacro("__TCE__");
5987  Builder.defineMacro("__TCE_V1__");
5988  }
5989  bool hasFeature(StringRef Feature) const override {
5990  return Feature == "tce";
5991  }
5992 
5993  void getTargetBuiltins(const Builtin::Info *&Records,
5994  unsigned &NumRecords) const override {}
5995  const char *getClobbers() const override {
5996  return "";
5997  }
5998  BuiltinVaListKind getBuiltinVaListKind() const override {
6000  }
6001  void getGCCRegNames(const char * const *&Names,
6002  unsigned &NumNames) const override {}
6003  bool validateAsmConstraint(const char *&Name,
6004  TargetInfo::ConstraintInfo &info) const override{
6005  return true;
6006  }
6007  void getGCCRegAliases(const GCCRegAlias *&Aliases,
6008  unsigned &NumAliases) const override {}
6009  };
6010 
6011 class BPFTargetInfo : public TargetInfo {
6012 public:
6013  BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6014  LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6015  SizeType = UnsignedLong;
6016  PtrDiffType = SignedLong;
6017  IntPtrType = SignedLong;
6018  IntMaxType = SignedLong;
6019  Int64Type = SignedLong;
6020  RegParmMax = 5;
6021  if (Triple.getArch() == llvm::Triple::bpfeb) {
6022  BigEndian = true;
6023  DescriptionString = "E-m:e-p:64:64-i64:64-n32:64-S128";
6024  } else {
6025  BigEndian = false;
6026  DescriptionString = "e-m:e-p:64:64-i64:64-n32:64-S128";
6027  }
6028  MaxAtomicPromoteWidth = 64;
6029  MaxAtomicInlineWidth = 64;
6030  TLSSupported = false;
6031  }
6032  void getTargetDefines(const LangOptions &Opts,
6033  MacroBuilder &Builder) const override {
6034  DefineStd(Builder, "bpf", Opts);
6035  Builder.defineMacro("__BPF__");
6036  }
6037  bool hasFeature(StringRef Feature) const override {
6038  return Feature == "bpf";
6039  }
6040 
6041  void getTargetBuiltins(const Builtin::Info *&Records,
6042  unsigned &NumRecords) const override {}
6043  const char *getClobbers() const override {
6044  return "";
6045  }
6046  BuiltinVaListKind getBuiltinVaListKind() const override {
6048  }
6049  void getGCCRegNames(const char * const *&Names,
6050  unsigned &NumNames) const override {
6051  Names = nullptr;
6052  NumNames = 0;
6053  }
6054  bool validateAsmConstraint(const char *&Name,
6055  TargetInfo::ConstraintInfo &info) const override {
6056  return true;
6057  }
6058  void getGCCRegAliases(const GCCRegAlias *&Aliases,
6059  unsigned &NumAliases) const override {
6060  Aliases = nullptr;
6061  NumAliases = 0;
6062  }
6063 };
6064 
6065 class MipsTargetInfoBase : public TargetInfo {
6066  virtual void setDescriptionString() = 0;
6067 
6068  static const Builtin::Info BuiltinInfo[];
6069  std::string CPU;
6070  bool IsMips16;
6071  bool IsMicromips;
6072  bool IsNan2008;
6073  bool IsSingleFloat;
6074  enum MipsFloatABI {
6075  HardFloat, SoftFloat
6076  } FloatABI;
6077  enum DspRevEnum {
6078  NoDSP, DSP1, DSP2
6079  } DspRev;
6080  bool HasMSA;
6081 
6082 protected:
6083  bool HasFP64;
6084  std::string ABI;
6085 
6086 public:
6087  MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
6088  const std::string &CPUStr)
6089  : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
6090  IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
6091  DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
6092  TheCXXABI.set(TargetCXXABI::GenericMIPS);
6093  }
6094 
6095  bool isNaN2008Default() const {
6096  return CPU == "mips32r6" || CPU == "mips64r6";
6097  }
6098 
6099  bool isFP64Default() const {
6100  return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
6101  }
6102 
6103  bool isNan2008() const override {
6104  return IsNan2008;
6105  }
6106 
6107  StringRef getABI() const override { return ABI; }
6108  bool setCPU(const std::string &Name) override {
6109  bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
6110  getTriple().getArch() == llvm::Triple::mipsel;
6111  CPU = Name;
6112  return llvm::StringSwitch<bool>(Name)
6113  .Case("mips1", IsMips32)
6114  .Case("mips2", IsMips32)
6115  .Case("mips3", true)
6116  .Case("mips4", true)
6117  .Case("mips5", true)
6118  .Case("mips32", IsMips32)
6119  .Case("mips32r2", IsMips32)
6120  .Case("mips32r3", IsMips32)
6121  .Case("mips32r5", IsMips32)
6122  .Case("mips32r6", IsMips32)
6123  .Case("mips64", true)
6124  .Case("mips64r2", true)
6125  .Case("mips64r3", true)
6126  .Case("mips64r5", true)
6127  .Case("mips64r6", true)
6128  .Case("octeon", true)
6129  .Default(false);
6130  }
6131  const std::string& getCPU() const { return CPU; }
6132  void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6133  if (CPU == "octeon")
6134  Features["mips64r2"] = Features["cnmips"] = true;
6135  else
6136  Features[CPU] = true;
6137  }
6138 
6139  void getTargetDefines(const LangOptions &Opts,
6140  MacroBuilder &Builder) const override {
6141  Builder.defineMacro("__mips__");
6142  Builder.defineMacro("_mips");
6143  if (Opts.GNUMode)
6144  Builder.defineMacro("mips");
6145 
6146  Builder.defineMacro("__REGISTER_PREFIX__", "");
6147 
6148  switch (FloatABI) {
6149  case HardFloat:
6150  Builder.defineMacro("__mips_hard_float", Twine(1));
6151  break;
6152  case SoftFloat:
6153  Builder.defineMacro("__mips_soft_float", Twine(1));
6154  break;
6155  }
6156 
6157  if (IsSingleFloat)
6158  Builder.defineMacro("__mips_single_float", Twine(1));
6159 
6160  Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
6161  Builder.defineMacro("_MIPS_FPSET",
6162  Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
6163 
6164  if (IsMips16)
6165  Builder.defineMacro("__mips16", Twine(1));
6166 
6167  if (IsMicromips)
6168  Builder.defineMacro("__mips_micromips", Twine(1));
6169 
6170  if (IsNan2008)
6171  Builder.defineMacro("__mips_nan2008", Twine(1));
6172 
6173  switch (DspRev) {
6174  default:
6175  break;
6176  case DSP1:
6177  Builder.defineMacro("__mips_dsp_rev", Twine(1));
6178  Builder.defineMacro("__mips_dsp", Twine(1));
6179  break;
6180  case DSP2:
6181  Builder.defineMacro("__mips_dsp_rev", Twine(2));
6182  Builder.defineMacro("__mips_dspr2", Twine(1));
6183  Builder.defineMacro("__mips_dsp", Twine(1));
6184  break;
6185  }
6186 
6187  if (HasMSA)
6188  Builder.defineMacro("__mips_msa", Twine(1));
6189 
6190  Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
6191  Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
6192  Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
6193 
6194  Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
6195  Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
6196  }
6197 
6198  void getTargetBuiltins(const Builtin::Info *&Records,
6199  unsigned &NumRecords) const override {
6200  Records = BuiltinInfo;
6202  }
6203  bool hasFeature(StringRef Feature) const override {
6204  return llvm::StringSwitch<bool>(Feature)
6205  .Case("mips", true)
6206  .Case("fp64", HasFP64)
6207  .Default(false);
6208  }
6209  BuiltinVaListKind getBuiltinVaListKind() const override {
6211  }
6212  void getGCCRegNames(const char * const *&Names,
6213  unsigned &NumNames) const override {
6214  static const char *const GCCRegNames[] = {
6215  // CPU register names
6216  // Must match second column of GCCRegAliases
6217  "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
6218  "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
6219  "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
6220  "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
6221  // Floating point register names
6222  "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
6223  "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
6224  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
6225  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
6226  // Hi/lo and condition register names
6227  "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
6228  "$fcc5","$fcc6","$fcc7",
6229  // MSA register names
6230  "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
6231  "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
6232  "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
6233  "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
6234  // MSA control register names
6235  "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
6236  "$msarequest", "$msamap", "$msaunmap"
6237  };
6238  Names = GCCRegNames;
6239  NumNames = llvm::array_lengthof(GCCRegNames);
6240  }
6241  void getGCCRegAliases(const GCCRegAlias *&Aliases,
6242  unsigned &NumAliases) const override = 0;
6243  bool validateAsmConstraint(const char *&Name,
6244  TargetInfo::ConstraintInfo &Info) const override {
6245  switch (*Name) {
6246  default:
6247  return false;
6248  case 'r': // CPU registers.
6249  case 'd': // Equivalent to "r" unless generating MIPS16 code.
6250  case 'y': // Equivalent to "r", backward compatibility only.
6251  case 'f': // floating-point registers.
6252  case 'c': // $25 for indirect jumps
6253  case 'l': // lo register
6254  case 'x': // hilo register pair
6255  Info.setAllowsRegister();
6256  return true;
6257  case 'I': // Signed 16-bit constant
6258  case 'J': // Integer 0
6259  case 'K': // Unsigned 16-bit constant
6260  case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
6261  case 'M': // Constants not loadable via lui, addiu, or ori
6262  case 'N': // Constant -1 to -65535
6263  case 'O': // A signed 15-bit constant
6264  case 'P': // A constant between 1 go 65535
6265  return true;
6266  case 'R': // An address that can be used in a non-macro load or store
6267  Info.setAllowsMemory();
6268  return true;
6269  case 'Z':
6270  if (Name[1] == 'C') { // An address usable by ll, and sc.
6271  Info.setAllowsMemory();
6272  Name++; // Skip over 'Z'.
6273  return true;
6274  }
6275  return false;
6276  }
6277  }
6278 
6279  std::string convertConstraint(const char *&Constraint) const override {
6280  std::string R;
6281  switch (*Constraint) {
6282  case 'Z': // Two-character constraint; add "^" hint for later parsing.
6283  if (Constraint[1] == 'C') {
6284  R = std::string("^") + std::string(Constraint, 2);
6285  Constraint++;
6286  return R;
6287  }
6288  break;
6289  }
6290  return TargetInfo::convertConstraint(Constraint);
6291  }
6292 
6293  const char *getClobbers() const override {
6294  // In GCC, $1 is not widely used in generated code (it's used only in a few
6295  // specific situations), so there is no real need for users to add it to
6296  // the clobbers list if they want to use it in their inline assembly code.
6297  //
6298  // In LLVM, $1 is treated as a normal GPR and is always allocatable during
6299  // code generation, so using it in inline assembly without adding it to the
6300  // clobbers list can cause conflicts between the inline assembly code and
6301  // the surrounding generated code.
6302  //
6303  // Another problem is that LLVM is allowed to choose $1 for inline assembly
6304  // operands, which will conflict with the ".set at" assembler option (which
6305  // we use only for inline assembly, in order to maintain compatibility with
6306  // GCC) and will also conflict with the user's usage of $1.
6307  //
6308  // The easiest way to avoid these conflicts and keep $1 as an allocatable
6309  // register for generated code is to automatically clobber $1 for all inline
6310  // assembly code.
6311  //
6312  // FIXME: We should automatically clobber $1 only for inline assembly code
6313  // which actually uses it. This would allow LLVM to use $1 for inline
6314  // assembly operands if the user's assembly code doesn't use it.
6315  return "~{$1}";
6316  }
6317 
6318  bool handleTargetFeatures(std::vector<std::string> &Features,
6319  DiagnosticsEngine &Diags) override {
6320  IsMips16 = false;
6321  IsMicromips = false;
6322  IsNan2008 = isNaN2008Default();
6323  IsSingleFloat = false;
6324  FloatABI = HardFloat;
6325  DspRev = NoDSP;
6326  HasFP64 = isFP64Default();
6327 
6328  for (std::vector<std::string>::iterator it = Features.begin(),
6329  ie = Features.end(); it != ie; ++it) {
6330  if (*it == "+single-float")
6331  IsSingleFloat = true;
6332  else if (*it == "+soft-float")
6333  FloatABI = SoftFloat;
6334  else if (*it == "+mips16")
6335  IsMips16 = true;
6336  else if (*it == "+micromips")
6337  IsMicromips = true;
6338  else if (*it == "+dsp")
6339  DspRev = std::max(DspRev, DSP1);
6340  else if (*it == "+dspr2")
6341  DspRev = std::max(DspRev, DSP2);
6342  else if (*it == "+msa")
6343  HasMSA = true;
6344  else if (*it == "+fp64")
6345  HasFP64 = true;
6346  else if (*it == "-fp64")
6347  HasFP64 = false;
6348  else if (*it == "+nan2008")
6349  IsNan2008 = true;
6350  else if (*it == "-nan2008")
6351  IsNan2008 = false;
6352  }
6353 
6354  setDescriptionString();
6355 
6356  return true;
6357  }
6358 
6359  int getEHDataRegisterNumber(unsigned RegNo) const override {
6360  if (RegNo == 0) return 4;
6361  if (RegNo == 1) return 5;
6362  return -1;
6363  }
6364 
6365  bool isCLZForZeroUndef() const override { return false; }
6366 };
6367 
6369 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6370 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6371  ALL_LANGUAGES },
6372 #include "clang/Basic/BuiltinsMips.def"
6373 };
6374 
6375 class Mips32TargetInfoBase : public MipsTargetInfoBase {
6376 public:
6377  Mips32TargetInfoBase(const llvm::Triple &Triple)
6378  : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
6379  SizeType = UnsignedInt;
6380  PtrDiffType = SignedInt;
6381  Int64Type = SignedLongLong;
6382  IntMaxType = Int64Type;
6383  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
6384  }
6385  bool setABI(const std::string &Name) override {
6386  if (Name == "o32" || Name == "eabi") {
6387  ABI = Name;
6388  return true;
6389  }
6390  return false;
6391  }
6392  void getTargetDefines(const LangOptions &Opts,
6393  MacroBuilder &Builder) const override {
6394  MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6395 
6396  Builder.defineMacro("__mips", "32");
6397  Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6398 
6399  const std::string& CPUStr = getCPU();
6400  if (CPUStr == "mips32")
6401  Builder.defineMacro("__mips_isa_rev", "1");
6402  else if (CPUStr == "mips32r2")
6403  Builder.defineMacro("__mips_isa_rev", "2");
6404  else if (CPUStr == "mips32r3")
6405  Builder.defineMacro("__mips_isa_rev", "3");
6406  else if (CPUStr == "mips32r5")
6407  Builder.defineMacro("__mips_isa_rev", "5");
6408  else if (CPUStr == "mips32r6")
6409  Builder.defineMacro("__mips_isa_rev", "6");
6410 
6411  if (ABI == "o32") {
6412  Builder.defineMacro("__mips_o32");
6413  Builder.defineMacro("_ABIO32", "1");
6414  Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6415  }
6416  else if (ABI == "eabi")
6417  Builder.defineMacro("__mips_eabi");
6418  else
6419  llvm_unreachable("Invalid ABI for Mips32.");
6420  }
6421  void getGCCRegAliases(const GCCRegAlias *&Aliases,
6422  unsigned &NumAliases) const override {
6423  static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6424  { { "at" }, "$1" },
6425  { { "v0" }, "$2" },
6426  { { "v1" }, "$3" },
6427  { { "a0" }, "$4" },
6428  { { "a1" }, "$5" },
6429  { { "a2" }, "$6" },
6430  { { "a3" }, "$7" },
6431  { { "t0" }, "$8" },
6432  { { "t1" }, "$9" },
6433  { { "t2" }, "$10" },
6434  { { "t3" }, "$11" },
6435  { { "t4" }, "$12" },
6436  { { "t5" }, "$13" },
6437  { { "t6" }, "$14" },
6438  { { "t7" }, "$15" },
6439  { { "s0" }, "$16" },
6440  { { "s1" }, "$17" },
6441  { { "s2" }, "$18" },
6442  { { "s3" }, "$19" },
6443  { { "s4" }, "$20" },
6444  { { "s5" }, "$21" },
6445  { { "s6" }, "$22" },
6446  { { "s7" }, "$23" },
6447  { { "t8" }, "$24" },
6448  { { "t9" }, "$25" },
6449  { { "k0" }, "$26" },
6450  { { "k1" }, "$27" },
6451  { { "gp" }, "$28" },
6452  { { "sp","$sp" }, "$29" },
6453  { { "fp","$fp" }, "$30" },
6454  { { "ra" }, "$31" }
6455  };
6456  Aliases = GCCRegAliases;
6457  NumAliases = llvm::array_lengthof(GCCRegAliases);
6458  }
6459 };
6460 
6461 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6462  void setDescriptionString() override {
6463  DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6464  }
6465 
6466 public:
6467  Mips32EBTargetInfo(const llvm::Triple &Triple)
6468  : Mips32TargetInfoBase(Triple) {
6469  }
6470  void getTargetDefines(const LangOptions &Opts,
6471  MacroBuilder &Builder) const override {
6472  DefineStd(Builder, "MIPSEB", Opts);
6473  Builder.defineMacro("_MIPSEB");
6474  Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6475  }
6476 };
6477 
6478 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6479  void setDescriptionString() override {
6480  DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6481  }
6482 
6483 public:
6484  Mips32ELTargetInfo(const llvm::Triple &Triple)
6485  : Mips32TargetInfoBase(Triple) {
6486  BigEndian = false;
6487  }
6488  void getTargetDefines(const LangOptions &Opts,
6489  MacroBuilder &Builder) const override {
6490  DefineStd(Builder, "MIPSEL", Opts);
6491  Builder.defineMacro("_MIPSEL");
6492  Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6493  }
6494 };
6495 
6496 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6497 public:
6498  Mips64TargetInfoBase(const llvm::Triple &Triple)
6499  : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6500  LongDoubleWidth = LongDoubleAlign = 128;
6501  LongDoubleFormat = &llvm::APFloat::IEEEquad;
6502  if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6503  LongDoubleWidth = LongDoubleAlign = 64;
6504  LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6505  }
6506  setN64ABITypes();
6507  SuitableAlign = 128;
6508  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6509  }
6510 
6511  void setN64ABITypes() {
6512  LongWidth = LongAlign = 64;
6513  PointerWidth = PointerAlign = 64;
6514  SizeType = UnsignedLong;
6515  PtrDiffType = SignedLong;
6516  Int64Type = SignedLong;
6517  IntMaxType = Int64Type;
6518  }
6519 
6520  void setN32ABITypes() {
6521  LongWidth = LongAlign = 32;
6522  PointerWidth = PointerAlign = 32;
6523  SizeType = UnsignedInt;
6524  PtrDiffType = SignedInt;
6525  Int64Type = SignedLongLong;
6526  IntMaxType = Int64Type;
6527  }
6528 
6529  bool setABI(const std::string &Name) override {
6530  if (Name == "n32") {
6531  setN32ABITypes();
6532  ABI = Name;
6533  return true;
6534  }
6535  if (Name == "n64") {
6536  setN64ABITypes();
6537  ABI = Name;
6538  return true;
6539  }
6540  return false;
6541  }
6542 
6543  void getTargetDefines(const LangOptions &Opts,
6544  MacroBuilder &Builder) const override {
6545  MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6546 
6547  Builder.defineMacro("__mips", "64");
6548  Builder.defineMacro("__mips64");
6549  Builder.defineMacro("__mips64__");
6550  Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6551 
6552  const std::string& CPUStr = getCPU();
6553  if (CPUStr == "mips64")
6554  Builder.defineMacro("__mips_isa_rev", "1");
6555  else if (CPUStr == "mips64r2")
6556  Builder.defineMacro("__mips_isa_rev", "2");
6557  else if (CPUStr == "mips64r3")
6558  Builder.defineMacro("__mips_isa_rev", "3");
6559  else if (CPUStr == "mips64r5")
6560  Builder.defineMacro("__mips_isa_rev", "5");
6561  else if (CPUStr == "mips64r6")
6562  Builder.defineMacro("__mips_isa_rev", "6");
6563 
6564  if (ABI == "n32") {
6565  Builder.defineMacro("__mips_n32");
6566  Builder.defineMacro("_ABIN32", "2");
6567  Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6568  }
6569  else if (ABI == "n64") {
6570  Builder.defineMacro("__mips_n64");
6571  Builder.defineMacro("_ABI64", "3");
6572  Builder.defineMacro("_MIPS_SIM", "_ABI64");
6573  }
6574  else
6575  llvm_unreachable("Invalid ABI for Mips64.");
6576  }
6577  void getGCCRegAliases(const GCCRegAlias *&Aliases,
6578  unsigned &NumAliases) const override {
6579  static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6580  { { "at" }, "$1" },
6581  { { "v0" }, "$2" },
6582  { { "v1" }, "$3" },
6583  { { "a0" }, "$4" },
6584  { { "a1" }, "$5" },
6585  { { "a2" }, "$6" },
6586  { { "a3" }, "$7" },
6587  { { "a4" }, "$8" },
6588  { { "a5" }, "$9" },
6589  { { "a6" }, "$10" },
6590  { { "a7" }, "$11" },
6591  { { "t0" }, "$12" },
6592  { { "t1" }, "$13" },
6593  { { "t2" }, "$14" },
6594  { { "t3" }, "$15" },
6595  { { "s0" }, "$16" },
6596  { { "s1" }, "$17" },
6597  { { "s2" }, "$18" },
6598  { { "s3" }, "$19" },
6599  { { "s4" }, "$20" },
6600  { { "s5" }, "$21" },
6601  { { "s6" }, "$22" },
6602  { { "s7" }, "$23" },
6603  { { "t8" }, "$24" },
6604  { { "t9" }, "$25" },
6605  { { "k0" }, "$26" },
6606  { { "k1" }, "$27" },
6607  { { "gp" }, "$28" },
6608  { { "sp","$sp" }, "$29" },
6609  { { "fp","$fp" }, "$30" },
6610  { { "ra" }, "$31" }
6611  };
6612  Aliases = GCCRegAliases;
6613  NumAliases = llvm::array_lengthof(GCCRegAliases);
6614  }
6615 
6616  bool hasInt128Type() const override { return true; }
6617 };
6618 
6619 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6620  void setDescriptionString() override {
6621  if (ABI == "n32")
6622  DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6623  else
6624  DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6625 
6626  }
6627 
6628 public:
6629  Mips64EBTargetInfo(const llvm::Triple &Triple)
6630  : Mips64TargetInfoBase(Triple) {}
6631  void getTargetDefines(const LangOptions &Opts,
6632  MacroBuilder &Builder) const override {
6633  DefineStd(Builder, "MIPSEB", Opts);
6634  Builder.defineMacro("_MIPSEB");
6635  Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6636  }
6637 };
6638 
6639 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6640  void setDescriptionString() override {
6641  if (ABI == "n32")
6642  DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6643  else
6644  DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6645  }
6646 public:
6647  Mips64ELTargetInfo(const llvm::Triple &Triple)
6648  : Mips64TargetInfoBase(Triple) {
6649  // Default ABI is n64.
6650  BigEndian = false;
6651  }
6652  void getTargetDefines(const LangOptions &Opts,
6653  MacroBuilder &Builder) const override {
6654  DefineStd(Builder, "MIPSEL", Opts);
6655  Builder.defineMacro("_MIPSEL");
6656  Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6657  }
6658 };
6659 
6660 class PNaClTargetInfo : public TargetInfo {
6661 public:
6662  PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6663  BigEndian = false;
6664  this->UserLabelPrefix = "";
6665  this->LongAlign = 32;
6666  this->LongWidth = 32;
6667  this->PointerAlign = 32;
6668  this->PointerWidth = 32;
6669  this->IntMaxType = TargetInfo::SignedLongLong;
6670  this->Int64Type = TargetInfo::SignedLongLong;
6671  this->DoubleAlign = 64;
6672  this->LongDoubleWidth = 64;
6673  this->LongDoubleAlign = 64;
6674  this->SizeType = TargetInfo::UnsignedInt;
6675  this->PtrDiffType = TargetInfo::SignedInt;
6676  this->IntPtrType = TargetInfo::SignedInt;
6677  this->RegParmMax = 0; // Disallow regparm
6678  }
6679 
6680  void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6681  }
6682  void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6683  Builder.defineMacro("__le32__");
6684  Builder.defineMacro("__pnacl__");
6685  }
6686  void getTargetDefines(const LangOptions &Opts,
6687  MacroBuilder &Builder) const override {
6688  getArchDefines(Opts, Builder);
6689  }
6690  bool hasFeature(StringRef Feature) const override {
6691  return Feature == "pnacl";
6692  }
6693  void getTargetBuiltins(const Builtin::Info *&Records,
6694  unsigned &NumRecords) const override {
6695  }
6696  BuiltinVaListKind getBuiltinVaListKind() const override {
6698  }
6699  void getGCCRegNames(const char * const *&Names,
6700  unsigned &NumNames) const override;
6701  void getGCCRegAliases(const GCCRegAlias *&Aliases,
6702  unsigned &NumAliases) const override;
6703  bool validateAsmConstraint(const char *&Name,
6704  TargetInfo::ConstraintInfo &Info) const override {
6705  return false;
6706  }
6707 
6708  const char *getClobbers() const override {
6709  return "";
6710  }
6711 };
6712 
6713 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6714  unsigned &NumNames) const {
6715  Names = nullptr;
6716  NumNames = 0;
6717 }
6718 
6719 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6720  unsigned &NumAliases) const {
6721  Aliases = nullptr;
6722  NumAliases = 0;
6723 }
6724 
6725 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
6726 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo {
6727 public:
6728  NaClMips32ELTargetInfo(const llvm::Triple &Triple) :
6729  Mips32ELTargetInfo(Triple) {
6730  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 0;
6731  }
6732 
6733  BuiltinVaListKind getBuiltinVaListKind() const override {
6735  }
6736 };
6737 
6738 class Le64TargetInfo : public TargetInfo {
6739  static const Builtin::Info BuiltinInfo[];
6740 
6741 public:
6742  Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6743  BigEndian = false;
6744  NoAsmVariants = true;
6745  LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6746  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6747  DescriptionString =
6748  "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6749  }
6750 
6751  void getTargetDefines(const LangOptions &Opts,
6752  MacroBuilder &Builder) const override {
6753  DefineStd(Builder, "unix", Opts);
6754  defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6755  Builder.defineMacro("__ELF__");
6756  }
6757  void getTargetBuiltins(const Builtin::Info *&Records,
6758  unsigned &NumRecords) const override {
6759  Records = BuiltinInfo;
6761  }
6762  BuiltinVaListKind getBuiltinVaListKind() const override {
6764  }
6765  const char *getClobbers() const override { return ""; }
6766  void getGCCRegNames(const char *const *&Names,
6767  unsigned &NumNames) const override {
6768  Names = nullptr;
6769  NumNames = 0;
6770  }
6771  void getGCCRegAliases(const GCCRegAlias *&Aliases,
6772  unsigned &NumAliases) const override {
6773  Aliases = nullptr;
6774  NumAliases = 0;
6775  }
6776  bool validateAsmConstraint(const char *&Name,
6777  TargetInfo::ConstraintInfo &Info) const override {
6778  return false;
6779  }
6780 
6781  bool hasProtectedVisibility() const override { return false; }
6782 };
6783 } // end anonymous namespace.
6784 
6786 #define BUILTIN(ID, TYPE, ATTRS) \
6787  { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6788 #include "clang/Basic/BuiltinsLe64.def"
6789 };
6790 
6791 namespace {
6792  static const unsigned SPIRAddrSpaceMap[] = {
6793  1, // opencl_global
6794  3, // opencl_local
6795  2, // opencl_constant
6796  4, // opencl_generic
6797  0, // cuda_device
6798  0, // cuda_constant
6799  0 // cuda_shared
6800  };
6801  class SPIRTargetInfo : public TargetInfo {
6802  public:
6803  SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6804  assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6805  "SPIR target must use unknown OS");
6806  assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6807  "SPIR target must use unknown environment type");
6808  BigEndian = false;
6809  TLSSupported = false;
6810  LongWidth = LongAlign = 64;
6811  AddrSpaceMap = &SPIRAddrSpaceMap;
6812  UseAddrSpaceMapMangling = true;
6813  // Define available target features
6814  // These must be defined in sorted order!
6815  NoAsmVariants = true;
6816  }
6817  void getTargetDefines(const LangOptions &Opts,
6818  MacroBuilder &Builder) const override {
6819  DefineStd(Builder, "SPIR", Opts);
6820  }
6821  bool hasFeature(StringRef Feature) const override {
6822  return Feature == "spir";
6823  }
6824 
6825  void getTargetBuiltins(const Builtin::Info *&Records,
6826  unsigned &NumRecords) const override {}
6827  const char *getClobbers() const override {
6828  return "";
6829  }
6830  void getGCCRegNames(const char * const *&Names,
6831  unsigned &NumNames) const override {}
6832  bool
6833  validateAsmConstraint(const char *&Name,
6834  TargetInfo::ConstraintInfo &info) const override {
6835  return true;
6836  }
6837  void getGCCRegAliases(const GCCRegAlias *&Aliases,
6838  unsigned &NumAliases) const override {}
6839  BuiltinVaListKind getBuiltinVaListKind() const override {
6841  }
6842 
6843  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6844  return (CC == CC_SpirFunction ||
6845  CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning;
6846  }
6847 
6848  CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
6849  return CC_SpirFunction;
6850  }
6851  };
6852 
6853 
6854  class SPIR32TargetInfo : public SPIRTargetInfo {
6855  public:
6856  SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6857  PointerWidth = PointerAlign = 32;
6858  SizeType = TargetInfo::UnsignedInt;
6859  PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6860  DescriptionString
6861  = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6862  "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6863  }
6864  void getTargetDefines(const LangOptions &Opts,
6865  MacroBuilder &Builder) const override {
6866  DefineStd(Builder, "SPIR32", Opts);
6867  }
6868  };
6869 
6870  class SPIR64TargetInfo : public SPIRTargetInfo {
6871  public:
6872  SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6873  PointerWidth = PointerAlign = 64;
6874  SizeType = TargetInfo::UnsignedLong;
6875  PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6876  DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6877  "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6878  }
6879  void getTargetDefines(const LangOptions &Opts,
6880  MacroBuilder &Builder) const override {
6881  DefineStd(Builder, "SPIR64", Opts);
6882  }
6883  };
6884 
6885 class XCoreTargetInfo : public TargetInfo {
6886  static const Builtin::Info BuiltinInfo[];
6887 public:
6888  XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6889  BigEndian = false;
6890  NoAsmVariants = true;
6891  LongLongAlign = 32;
6892  SuitableAlign = 32;
6893  DoubleAlign = LongDoubleAlign = 32;
6894  SizeType = UnsignedInt;
6895  PtrDiffType = SignedInt;
6896  IntPtrType = SignedInt;
6897  WCharType = UnsignedChar;
6898  WIntType = UnsignedInt;
6899  UseZeroLengthBitfieldAlignment = true;
6900  DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6901  "-f64:32-a:0:32-n32";
6902  }
6903  void getTargetDefines(const LangOptions &Opts,
6904  MacroBuilder &Builder) const override {
6905  Builder.defineMacro("__XS1B__");
6906  }
6907  void getTargetBuiltins(const Builtin::Info *&Records,
6908  unsigned &NumRecords) const override {
6909  Records = BuiltinInfo;
6911  }
6912  BuiltinVaListKind getBuiltinVaListKind() const override {
6914  }
6915  const char *getClobbers() const override {
6916  return "";
6917  }
6918  void getGCCRegNames(const char * const *&Names,
6919  unsigned &NumNames) const override {
6920  static const char * const GCCRegNames[] = {
6921  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6922  "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
6923  };
6924  Names = GCCRegNames;
6925  NumNames = llvm::array_lengthof(GCCRegNames);
6926  }
6927  void getGCCRegAliases(const GCCRegAlias *&Aliases,
6928  unsigned &NumAliases) const override {
6929  Aliases = nullptr;
6930  NumAliases = 0;
6931  }
6932  bool validateAsmConstraint(const char *&Name,
6933  TargetInfo::ConstraintInfo &Info) const override {
6934  return false;
6935  }
6936  int getEHDataRegisterNumber(unsigned RegNo) const override {
6937  // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6938  return (RegNo < 2)? RegNo : -1;
6939  }
6940 };
6941 
6943 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6944 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6945  ALL_LANGUAGES },
6946 #include "clang/Basic/BuiltinsXCore.def"
6947 };
6948 } // end anonymous namespace.
6949 
6950 namespace {
6951 // x86_32 Android target
6952 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
6953 public:
6954  AndroidX86_32TargetInfo(const llvm::Triple &Triple)
6955  : LinuxTargetInfo<X86_32TargetInfo>(Triple) {
6956  SuitableAlign = 32;
6957  LongDoubleWidth = 64;
6958  LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6959  }
6960 };
6961 } // end anonymous namespace
6962 
6963 namespace {
6964 // x86_64 Android target
6965 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
6966 public:
6967  AndroidX86_64TargetInfo(const llvm::Triple &Triple)
6968  : LinuxTargetInfo<X86_64TargetInfo>(Triple) {
6969  LongDoubleFormat = &llvm::APFloat::IEEEquad;
6970  }
6971 
6972  bool useFloat128ManglingForLongDouble() const override {
6973  return true;
6974  }
6975 };
6976 } // end anonymous namespace
6977 
6978 
6979 //===----------------------------------------------------------------------===//
6980 // Driver code
6981 //===----------------------------------------------------------------------===//
6982 
6983 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6984  llvm::Triple::OSType os = Triple.getOS();
6985 
6986  switch (Triple.getArch()) {
6987  default:
6988  return nullptr;
6989 
6990  case llvm::Triple::xcore:
6991  return new XCoreTargetInfo(Triple);
6992 
6993  case llvm::Triple::hexagon:
6994  return new HexagonTargetInfo(Triple);
6995 
6996  case llvm::Triple::aarch64:
6997  if (Triple.isOSDarwin())
6998  return new DarwinAArch64TargetInfo(Triple);
6999 
7000  switch (os) {
7001  case llvm::Triple::FreeBSD:
7002  return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
7003  case llvm::Triple::Linux:
7004  return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
7005  case llvm::Triple::NetBSD:
7006  return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
7007  default:
7008  return new AArch64leTargetInfo(Triple);
7009  }
7010 
7011  case llvm::Triple::aarch64_be:
7012  switch (os) {
7013  case llvm::Triple::FreeBSD:
7014  return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
7015  case llvm::Triple::Linux:
7016  return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
7017  case llvm::Triple::NetBSD:
7018  return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
7019  default:
7020  return new AArch64beTargetInfo(Triple);
7021  }
7022 
7023  case llvm::Triple::arm:
7024  case llvm::Triple::thumb:
7025  if (Triple.isOSBinFormatMachO())
7026  return new DarwinARMTargetInfo(Triple);
7027 
7028  switch (os) {
7029  case llvm::Triple::Linux:
7030  return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
7031  case llvm::Triple::FreeBSD:
7032  return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
7033  case llvm::Triple::NetBSD:
7034  return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
7035  case llvm::Triple::OpenBSD:
7036  return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
7037  case llvm::Triple::Bitrig:
7038  return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
7039  case llvm::Triple::RTEMS:
7040  return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
7041  case llvm::Triple::NaCl:
7042  return new NaClTargetInfo<ARMleTargetInfo>(Triple);
7043  case llvm::Triple::Win32:
7044  switch (Triple.getEnvironment()) {
7045  case llvm::Triple::Itanium:
7046  return new ItaniumWindowsARMleTargetInfo(Triple);
7047  case llvm::Triple::MSVC:
7048  default: // Assume MSVC for unknown environments
7049  return new MicrosoftARMleTargetInfo(Triple);
7050  }
7051  default:
7052  return new ARMleTargetInfo(Triple);
7053  }
7054 
7055  case llvm::Triple::armeb:
7056  case llvm::Triple::thumbeb:
7057  if (Triple.isOSDarwin())
7058  return new DarwinARMTargetInfo(Triple);
7059 
7060  switch (os) {
7061  case llvm::Triple::Linux:
7062  return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
7063  case llvm::Triple::FreeBSD:
7064  return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
7065  case llvm::Triple::NetBSD:
7066  return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
7067  case llvm::Triple::OpenBSD:
7068  return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
7069  case llvm::Triple::Bitrig:
7070  return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
7071  case llvm::Triple::RTEMS:
7072  return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
7073  case llvm::Triple::NaCl:
7074  return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
7075  default:
7076  return new ARMbeTargetInfo(Triple);
7077  }
7078 
7079  case llvm::Triple::bpfeb:
7080  case llvm::Triple::bpfel:
7081  return new BPFTargetInfo(Triple);
7082 
7083  case llvm::Triple::msp430:
7084  return new MSP430TargetInfo(Triple);
7085 
7086  case llvm::Triple::mips:
7087  switch (os) {
7088  case llvm::Triple::Linux:
7089  return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
7090  case llvm::Triple::RTEMS:
7091  return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
7092  case llvm::Triple::FreeBSD:
7093  return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7094  case llvm::Triple::NetBSD:
7095  return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7096  default:
7097  return new Mips32EBTargetInfo(Triple);
7098  }
7099 
7100  case llvm::Triple::mipsel:
7101  switch (os) {
7102  case llvm::Triple::Linux:
7103  return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
7104  case llvm::Triple::RTEMS:
7105  return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
7106  case llvm::Triple::FreeBSD:
7107  return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7108  case llvm::Triple::NetBSD:
7109  return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7110  case llvm::Triple::NaCl:
7111  return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple);
7112  default:
7113  return new Mips32ELTargetInfo(Triple);
7114  }
7115 
7116  case llvm::Triple::mips64:
7117  switch (os) {
7118  case llvm::Triple::Linux:
7119  return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
7120  case llvm::Triple::RTEMS:
7121  return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
7122  case llvm::Triple::FreeBSD:
7123  return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7124  case llvm::Triple::NetBSD:
7125  return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7126  case llvm::Triple::OpenBSD:
7127  return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7128  default:
7129  return new Mips64EBTargetInfo(Triple);
7130  }
7131 
7132  case llvm::Triple::mips64el:
7133  switch (os) {
7134  case llvm::Triple::Linux:
7135  return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
7136  case llvm::Triple::RTEMS:
7137  return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
7138  case llvm::Triple::FreeBSD:
7139  return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7140  case llvm::Triple::NetBSD:
7141  return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7142  case llvm::Triple::OpenBSD:
7143  return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7144  default:
7145  return new Mips64ELTargetInfo(Triple);
7146  }
7147 
7148  case llvm::Triple::le32:
7149  switch (os) {
7150  case llvm::Triple::NaCl:
7151  return new NaClTargetInfo<PNaClTargetInfo>(Triple);
7152  default:
7153  return nullptr;
7154  }
7155 
7156  case llvm::Triple::le64:
7157  return new Le64TargetInfo(Triple);
7158 
7159  case llvm::Triple::ppc:
7160  if (Triple.isOSDarwin())
7161  return new DarwinPPC32TargetInfo(Triple);
7162  switch (os) {
7163  case llvm::Triple::Linux:
7164  return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
7165  case llvm::Triple::FreeBSD:
7166  return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
7167  case llvm::Triple::NetBSD:
7168  return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
7169  case llvm::Triple::OpenBSD:
7170  return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
7171  case llvm::Triple::RTEMS:
7172  return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
7173  default:
7174  return new PPC32TargetInfo(Triple);
7175  }
7176 
7177  case llvm::Triple::ppc64:
7178  if (Triple.isOSDarwin())
7179  return new DarwinPPC64TargetInfo(Triple);
7180  switch (os) {
7181  case llvm::Triple::Linux:
7182  return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7183  case llvm::Triple::Lv2:
7184  return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
7185  case llvm::Triple::FreeBSD:
7186  return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
7187  case llvm::Triple::NetBSD:
7188  return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7189  default:
7190  return new PPC64TargetInfo(Triple);
7191  }
7192 
7193  case llvm::Triple::ppc64le:
7194  switch (os) {
7195  case llvm::Triple::Linux:
7196  return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7197  case llvm::Triple::NetBSD:
7198  return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7199  default:
7200  return new PPC64TargetInfo(Triple);
7201  }
7202 
7203  case llvm::Triple::nvptx:
7204  return new NVPTX32TargetInfo(Triple);
7205  case llvm::Triple::nvptx64:
7206  return new NVPTX64TargetInfo(Triple);
7207 
7208  case llvm::Triple::amdgcn:
7209  case llvm::Triple::r600:
7210  return new AMDGPUTargetInfo(Triple);
7211 
7212  case llvm::Triple::sparc:
7213  switch (os) {
7214  case llvm::Triple::Linux:
7215  return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
7216  case llvm::Triple::Solaris:
7217  return new SolarisTargetInfo<SparcV8TargetInfo>(Triple);
7218  case llvm::Triple::NetBSD:
7219  return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
7220  case llvm::Triple::OpenBSD:
7221  return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
7222  case llvm::Triple::RTEMS:
7223  return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
7224  default:
7225  return new SparcV8TargetInfo(Triple);
7226  }
7227 
7228  // The 'sparcel' architecture copies all the above cases except for Solaris.
7229  case llvm::Triple::sparcel:
7230  switch (os) {
7231  case llvm::Triple::Linux:
7232  return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple);
7233  case llvm::Triple::NetBSD:
7234  return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7235  case llvm::Triple::OpenBSD:
7236  return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7237  case llvm::Triple::RTEMS:
7238  return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple);
7239  default:
7240  return new SparcV8elTargetInfo(Triple);
7241  }
7242 
7243  case llvm::Triple::sparcv9:
7244  switch (os) {
7245  case llvm::Triple::Linux:
7246  return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
7247  case llvm::Triple::Solaris:
7248  return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
7249  case llvm::Triple::NetBSD:
7250  return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
7251  case llvm::Triple::OpenBSD:
7252  return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
7253  case llvm::Triple::FreeBSD:
7254  return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
7255  default:
7256  return new SparcV9TargetInfo(Triple);
7257  }
7258 
7259  case llvm::Triple::systemz:
7260  switch (os) {
7261  case llvm::Triple::Linux:
7262  return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
7263  default:
7264  return new SystemZTargetInfo(Triple);
7265  }
7266 
7267  case llvm::Triple::tce:
7268  return new TCETargetInfo(Triple);
7269 
7270  case llvm::Triple::x86:
7271  if (Triple.isOSDarwin())
7272  return new DarwinI386TargetInfo(Triple);
7273 
7274  switch (os) {
7275  case llvm::Triple::CloudABI:
7276  return new CloudABITargetInfo<X86_32TargetInfo>(Triple);
7277  case llvm::Triple::Linux: {
7278  switch (Triple.getEnvironment()) {
7279  default:
7280  return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
7281  case llvm::Triple::Android:
7282  return new AndroidX86_32TargetInfo(Triple);
7283  }
7284  }
7285  case llvm::Triple::DragonFly:
7286  return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
7287  case llvm::Triple::NetBSD:
7288  return new NetBSDI386TargetInfo(Triple);
7289  case llvm::Triple::OpenBSD:
7290  return new OpenBSDI386TargetInfo(Triple);
7291  case llvm::Triple::Bitrig:
7292  return new BitrigI386TargetInfo(Triple);
7293  case llvm::Triple::FreeBSD:
7294  return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7295  case llvm::Triple::KFreeBSD:
7296  return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7297  case llvm::Triple::Minix:
7298  return new MinixTargetInfo<X86_32TargetInfo>(Triple);
7299  case llvm::Triple::Solaris:
7300  return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
7301  case llvm::Triple::Win32: {
7302  switch (Triple.getEnvironment()) {
7303  case llvm::Triple::Cygnus:
7304  return new CygwinX86_32TargetInfo(Triple);
7305  case llvm::Triple::GNU:
7306  return new MinGWX86_32TargetInfo(Triple);
7307  case llvm::Triple::Itanium:
7308  case llvm::Triple::MSVC:
7309  default: // Assume MSVC for unknown environments
7310  return new MicrosoftX86_32TargetInfo(Triple);
7311  }
7312  }
7313  case llvm::Triple::Haiku:
7314  return new HaikuX86_32TargetInfo(Triple);
7315  case llvm::Triple::RTEMS:
7316  return new RTEMSX86_32TargetInfo(Triple);
7317  case llvm::Triple::NaCl:
7318  return new NaClTargetInfo<X86_32TargetInfo>(Triple);
7319  default:
7320  return new X86_32TargetInfo(Triple);
7321  }
7322 
7323  case llvm::Triple::x86_64:
7324  if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
7325  return new DarwinX86_64TargetInfo(Triple);
7326 
7327  switch (os) {
7328  case llvm::Triple::CloudABI:
7329  return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
7330  case llvm::Triple::Linux: {
7331  switch (Triple.getEnvironment()) {
7332  default:
7333  return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
7334  case llvm::Triple::Android:
7335  return new AndroidX86_64TargetInfo(Triple);
7336  }
7337  }
7338  case llvm::Triple::DragonFly:
7339  return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
7340  case llvm::Triple::NetBSD:
7341  return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
7342  case llvm::Triple::OpenBSD:
7343  return new OpenBSDX86_64TargetInfo(Triple);
7344  case llvm::Triple::Bitrig:
7345  return new BitrigX86_64TargetInfo(Triple);
7346  case llvm::Triple::FreeBSD:
7347  return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7348  case llvm::Triple::KFreeBSD:
7349  return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7350  case llvm::Triple::Solaris:
7351  return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
7352  case llvm::Triple::Win32: {
7353  switch (Triple.getEnvironment()) {
7354  case llvm::Triple::GNU:
7355  return new MinGWX86_64TargetInfo(Triple);
7356  case llvm::Triple::MSVC:
7357  default: // Assume MSVC for unknown environments
7358  return new MicrosoftX86_64TargetInfo(Triple);
7359  }
7360  }
7361  case llvm::Triple::NaCl:
7362  return new NaClTargetInfo<X86_64TargetInfo>(Triple);
7363  case llvm::Triple::PS4:
7364  return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
7365  default:
7366  return new X86_64TargetInfo(Triple);
7367  }
7368 
7369  case llvm::Triple::spir: {
7370  if (Triple.getOS() != llvm::Triple::UnknownOS ||
7371  Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7372  return nullptr;
7373  return new SPIR32TargetInfo(Triple);
7374  }
7375  case llvm::Triple::spir64: {
7376  if (Triple.getOS() != llvm::Triple::UnknownOS ||
7377  Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7378  return nullptr;
7379  return new SPIR64TargetInfo(Triple);
7380  }
7381  }
7382 }
7383 
7384 /// CreateTargetInfo - Return the target info object for the specified target
7385 /// triple.
7386 TargetInfo *
7388  const std::shared_ptr<TargetOptions> &Opts) {
7389  llvm::Triple Triple(Opts->Triple);
7390 
7391  // Construct the target
7392  std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
7393  if (!Target) {
7394  Diags.Report(diag::err_target_unknown_triple) << Triple.str();
7395  return nullptr;
7396  }
7397  Target->TargetOpts = Opts;
7398 
7399  // Set the target CPU if specified.
7400  if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
7401  Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
7402  return nullptr;
7403  }
7404 
7405  // Set the target ABI if specified.
7406  if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
7407  Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
7408  return nullptr;
7409  }
7410 
7411  // Set the fp math unit.
7412  if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
7413  Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
7414  return nullptr;
7415  }
7416 
7417  // Compute the default target features, we need the target to handle this
7418  // because features may have dependencies on one another.
7419  llvm::StringMap<bool> Features;
7420  Target->getDefaultFeatures(Features);
7421 
7422  // Apply the user specified deltas.
7423  for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
7424  I < N; ++I) {
7425  const char *Name = Opts->FeaturesAsWritten[I].c_str();
7426  // Apply the feature via the target.
7427  bool Enabled = Name[0] == '+';
7428  Target->setFeatureEnabled(Features, Name + 1, Enabled);
7429  }
7430 
7431  // Add the features to the compile options.
7432  //
7433  // FIXME: If we are completely confident that we have the right set, we only
7434  // need to pass the minuses.
7435  Opts->Features.clear();
7436  for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
7437  ie = Features.end(); it != ie; ++it)
7438  Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
7439  if (!Target->handleTargetFeatures(Opts->Features, Diags))
7440  return nullptr;
7441 
7442  return Target.release();
7443 }
Defines the clang::MacroBuilder utility class.
static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder)
Definition: Targets.cpp:3706
Represents a version number in the form major[.minor[.subminor[.build]]].
Definition: VersionTuple.h:26
SanitizerSet Sanitize
Set of enabled sanitizers.
Definition: LangOptions.h:79
static const Builtin::Info BuiltinInfo[]
Definition: Builtins.cpp:22
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1118
static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, const llvm::Triple &Triple, StringRef &PlatformName, VersionTuple &PlatformMinVersion)
Definition: Targets.cpp:88
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:48
uint32_t Offset
Definition: CacheTokens.cpp:43
static void DefineStd(MacroBuilder &Builder, StringRef MacroName, const LangOptions &Opts)
Definition: Targets.cpp:42
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:135
static TargetInfo * AllocateTarget(const llvm::Triple &Triple)
Definition: Targets.cpp:6983
virtual std::string convertConstraint(const char *&Constraint) const
static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning=true)
Definition: Targets.cpp:58
Exposes information about the current target.
Defines the clang::LangOptions interface.
static TargetInfo * CreateTargetInfo(DiagnosticsEngine &Diags, const std::shared_ptr< TargetOptions > &Opts)
Construct a target for the given options.
Definition: Targets.cpp:7387
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:204
Enumerates target-specific builtins in their own namespaces within namespace clang.
#define false
Definition: stdbool.h:33
Defines the clang::TargetOptions class.
Defines the Diagnostic-related interfaces.
static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder)
Definition: Targets.cpp:3730
bool has(SanitizerMask K) const
Check if a certain (single) sanitizer is enabled.
Definition: Sanitizers.h:52
bool isCompatibleWithMSVC(MSVCMajorVersion MajorVersion) const
Definition: LangOptions.h:130
BoundNodesTreeBuilder *const Builder
Defines the clang::TargetInfo interface.
void defineMacro(const Twine &Name, const Twine &Value="1")
Append a #define line for macro of the form "\#define Name Value\n".
Definition: MacroBuilder.h:30
#define true
Definition: stdbool.h:32
Defines enum values for all the target-independent builtin functions.