Yes, both are possible at least in principle, but the details matter. When it comes to parallelization, almost everything in LPCNet can be done in parallel but because the network runs once per sample (at 16 kHz), you need to be able to handle a lot of synchronization points (in the order of 100k per second) to have something that's worth it. Also, since a lot of the data comes from the cache, you don't want the relevant cache level (typically the L2) to be shared across cores.

When it comes to FPGAs, I suspect LPCNet can be implemented quite efficiently, bot only if the weights of the sample rate network can fit on the chip and not have to come from external memory. That means having around 100k-200k internal storage.