Vybhava S

Common Resource Block (CRB) in 5G-NR 1. CRBs are set of RBs which occupy channel bandwidth and they are defined for each subcarrier spacing. 2. CRBs provide the RB numbering throughout the carrier bandwidth while PRBs provide RB numbering within each BWP. 3. They are numbered from 0 in upward direction where CRB 0 is located at lower side of Channel Bandwidth. 4. The CRBs associated with each and every SCS are aligned at Point A  i.e., the center of subcarrier 0 of CRB 0 for each subcarrier spacing coincides with Point A. 5. From figure, the CRB edges for different SCS are not aligned. The CRB edge with SCS = 2∆f is shifted by ∆f kHz as compared to CRB edge with SCS= ∆f. For example, the CRB edge with SCS= 30kHz is shifted by 7.5kHz as compared to CRB edge with SCS= 15kHz. 6. UE determines the position of 'Point A' using ARFCN provided by SIB1 or dedicated signalling from gNB. SIB1 provides the FrequencyInfoDL-SIB parameter including IE "offset to carrier value" specifying the number of RBs between 'Point A' and subcarrier 0 and also IE 'carrierBandwidth' that specifics the number of RBs which are available.  #5g #5gnetwork #5gnr #communication #5gtechnology

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MEMORY DESIGN & VERIFICATION Memory is an integral part of any SoC design. Memory can be in different forms like: Registers Cache ROM RAM Secondary memory, etc. Today let's focus on designing & verifying a memory design. Up for the challenge? Link in COMMENT #rtldesign #rtl #digital #digitalelectronics #digitalelectronics #lectures #computerengineering #computerarchitecture #vlsidesign #vlsi #vlsitraining #vlsijobs #vlsiprojects #verification #verificationengineer #physicaldesign #pd #physicaldesignengineer #semiconductor #semiconductorindustry #career #careerdevelopment #careerguidance #resume #resumebuilding #resumereview #mentor #mentorship #vlsihelpinghands #switispeaks #switipinjani #coding #codinglife #codingtutorial #codingtips #codingjourney #programming #programmer #education #computer #guidance #interview #selfimprovement #selfdevelopment #motivation #careerdevelopment #careers #learning #sv #uvm #systemverilog #soc #ip #asics #cpu #processor #hardwaredescriptionlanguage #cpu #gpu #graphics #supercomputer #tutorial

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From Light Switches to Laptops: How logic Gates Define the World of Digital VLSI Design? 🚀 Imagine tiny switches that can be turned on or off with electricity. These are basically logic gates, the building blocks of digital circuits. They take electrical signals as inputs (like a light switch being flipped on or off), perform a simple logical operation on those signals, and then output a new signal based on that operation. 🚀 Logic gates perform basic operations like AND, OR, and NOT: AND Gate: The output is on (1) ONLY if ALL inputs are on (1). OR Gate: The output is on (1) if ANY input is on (1). NOT Gate: The output is the inverse of the input, flipping the signal (if the input is 1, the output is 0, and vice versa). By combining these simple operations in different ways, you can create complex digital circuits for all sorts of functions in a computer or device. 🚀 Light switch: Imagine a simple light controlled by two switches. You want the light to be on only if BOTH switches are flipped on (think of a hallway light needing two switches at either end). This can be achieved with an AND gate. One input comes from each switch, and the output from the AND gate goes to the light bulb. Only when both inputs (switches) are on (flipped) will the output (light) turn on. 🚀 Security system: Let's say you have a security system with a motion sensor and a door sensor. You want an alarm to sound if EITHER the motion sensor detects movement OR the door is opened. This can be built with an OR gate. One input comes from the motion sensor and the other from the door sensor. If EITHER input (sensor) detects something (goes on), the output from the OR gate will trigger the alarm. 🚀 Traffic light controller: This one requires a combination of gates. We can use an AND gate to ensure both the pedestrian button is pressed AND there are no cars detected to allow pedestrian crossing. Similarly, we can use an OR gate to ensure EITHER a timer runs out OR a car is detected to switch the light to green for traffic. 🚀 Basic arithmetic: Logic gates can even be used for simple math. By combining AND, OR, and NOT gates in specific ways, you can create circuits that perform operations like addition or subtraction on binary numbers (0s and 1s). These are the building blocks for more complex arithmetic units in computers. A detailed post is in comments. For all semiconductor and AI related content, follow TechoVedas

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Project 13: Serial Adder (108 Advanced RTL Projects) 1. Project Overview A serial adder processes binary numbers sequentially, performing bit-by-bit addition over multiple clock cycles. 2. Teammates Gati Goyal Ayush Jain NIKUNJ AGRAWAL 3. Low Area & Power Efficiency Consumes fewer hardware resources (gates, flip-flops) compared to parallel adders, making it ideal for low-power designs. 4. Operation Utilizes a full adder with shift registers and a clock signal to sequentially add operands and propagate carry. 5. SystemVerilog Design RTL design implemented in SystemVerilog, leveraging modular components like full adders and registers. 6. Test Bench Testbench validates the serial adder's functionality with various binary inputs and tests for correct carry propagation. 7. Simulation Results Simulation waveforms demonstrate bitwise addition and the sequential carry-forward mechanism. 8. Synthesis The synthesized design shows optimized resource usage, highlighting minimal gate count and power consumption. 9. Applications Commonly used in embedded systems, signal processing units, and low-cost IoT devices. 10. Industry Use Widely adopted by companies such as Intel Corporation , Arm , Texas Instruments Silicon Labs , and AMD for power-sensitive designs. Tags: #SerialAdder #RTLDesign #SystemVerilog #DigitalLogic #LowPowerDesign #EmbeddedSystems #VLSIDesign #FPGA #Synthesis

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Howdy, Gangs of VLSI! Logic equivalence checking entails the comparison of the logical functionality between two designs, which may be represented in diverse formats like RTL descriptions, gate-level netlists, or schematic diagrams. Its objective is to ensure that the fundamental logical behaviour remains consistent despite variations in implementation specifics or optimizations. This verification confirms that both designs yield identical truth tables or logic equations, affirming their equivalence in functionality. Here's the link to the article I wrote on what is LEC and tools used for LEC. Read “Logic Equivalence Check“ by superstar on Medium: https://lnkd.in/gFvXdThW #vlsi #synopsys #physicaldesign

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MAC-layer Scheduling in 5G-NR 1. gNB decides which UE should get resource in time and frequency domain and MAC-layer is responsible for this scheduling. 3GPP is not standardizing the algorithms hence vendors can use there own to satisfy the needs. 2. Scheduler Algorithm optimization is required to satisfy QOS requirements as during connection with gNB each UE has a QFI(Quality of service flow). So based on different 5QI values with certain demand to resource type, priority level, latency etc., the scheduler algorithms are defined. 3. Few Common Scheduler Algorithms are: a) Round Robin --> In this algorithm, there is no priority between incoming packets from different users, simple funda is First income, First gets the resource. Only problem with this algo is in poor radio condition with lot of users. b) Maximum CQI --> CQI is transmitted to UE periodically, based on this scheduler appoints priority in queue and resources are assigned accordingly. 4. As compared to LTE, where DCI are transported by CCE (Control Channel Element) where 1CCE= 9 REG, and 1 REG=4 Resource Elements there value of CCE depends on radio conditions of UE but in 5G NR DCI is transmitted via CORESET. 5. Resource allocation is done by taking into account UE radio condition, SINR, buffer Status, bandwidth, carrier aggregation (CA) etc. #5g #5gtechnology #5gnr #network #5gconnectivity #mac

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AXI is a multi channel bus which is popularly used as an interfacing protocol between multiple IP's and is useful both in RTL design and ASIC Verification. Below are the key concepts which are needed to understand AXI protocol in depth. [1] Difference between AXI and AHB. Number of Channels used in AXI. Why there is no separate Read response on AXI. [2] What are out of order and outstanding transaction in AXI. [3] What is the address boundary that slave can access in AXI. [4] Transfer mechanism for Write / Read with / without delay. [5] Valid and Ready hand shaking mechanism. What is deadlock condition. How to overcome it. [6] Difference b/w Incrementing and Wrapping Burst. What is a Fixed Burst type. [7] Difference b/w Bufferable and Cacheable type of transaction in AXI. [8] Complete understanding of Exclusive access phenomenon. Difference b/w OKAY and EXOKAY response. [9] What is a Locked access in AXI3. Why it is removed in AXI4. [10] What are the conditions for SLVERR and DECERR. [11] What is a QOS support for AXI4. What are the significance of AxREGION and AxUSER in AXI4. [12] Difference b/w AXI3 and AXI4. [13] What is a write interleaving method in AXI3 and why it's removed in AXI4. #vlsi #asic #semiconductorindustry #electricalengineering

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#100DaysofRTL Day-94 And construct in SVA Hello all, In SystemVerilog Assertions (SVA), the AND construct allows you to combine multiple sequences or conditions that must all hold true simultaneously. It is used to assert that several conditions are satisfied concurrently during a specific cycle or over a sequence of cycles. The AND construct is used with the and keyword in SVA. It allows you to combine multiple sequences or boolean expressions so that all of them must be true at the same time for the assertion to pass. The AND construct in SVA allows you to assert that multiple sequences or conditions must all hold true simultaneously. It's a powerful way to express the requirement that several things must happen at the same time in your design, making it essential for complex assertions and formal verification. 👉 check my github repo for the verilog code: https://lnkd.in/gd7UNcFC 👉 Hope you learnt something today #100daysofrtl #intel #verilog #linux #texasinstruments #rtldesign #synopsys #cisco #amd #digital #github #githubactions #github #communication #verilog #systemverilog #verification #intel #synopsys #cadence #nxp #mavensilicon #design #qualcomm #verificationengineer #amd #arm #pentium #vlsi #100codesofrtl #systemverilog #verilogcoding #verilog #rtldesign #designverification #intel #education #passionate #vlsi #vlsipassion #brandambassador #coding #rtlcoding #uvm #vlsidesign #perl #pythonprogramming #100codes #codingchallenge #alsemi #agnisys #greensemi #intel #jntu #studentslife #data #like #start #verificationacademy

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Advanced High-performance Bus (AHB) is a part of AMBA bus which is used as a communication and Interface protocol in Subsystem / IP / SOC based design and is essential for both RTL and ASIC Verification in VLSI. Below are the important concepts that are needed to learn AHB protocol. [1] Role of Arbiter and Decoder in AMBA AHB. [2] Different arbitration mechanism in AHB. (Ex: Round Robin, Priority access, etc) [3] Multi Master - Slave interconnection scheme in AHB. [4] Difference between Incrementing and Wrapping Burst. [5] What is an address and data phase in AHB. Why data phase can accomodate multiple cycle. Waveform for Basic transfer operation. [6] Total maximum No. Of wait states can be inserted as a delay in AHB cycles. [7] Difference between Sequential and Non-seqiential transfer. Role of Idle cycle. [8] What is the role of default Slave and when it is needed. [9] How the address decoding operation execute in AHB. [10] Early Burst termination mechanism. [11] What are the different response mechanism scheme in AHB. Role of HreadyIn and HreadyOut signal. [12] What is the difference between Split and Retry operation. Why OK response execute in single cycle and Error, Retry and Split need at least two cycles. [13] How the arbiter decide which Master to grant access to the bus. Role of HGRANTx and HBUSREQx signal. [14] Role of default master and why it only execute Idle cycle. [15] Locked transfer operation in AHB. [16] How to prevent deadlock when multiple master try to access the bus. How AHB handles multiple split transfer. [17] Operation of AHB bridge in AHB to APB interface. [18] Limit of boundary access in AHB. What will happen if the slave try to access out of bound address range. [19] No. of channels in AHB and it's pipelined architecture. [20] What is the role of dummy master in AHB. #vlsi #asic #semiconductorindustry #electricalengineering

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Discover the essence of practical physical synthesis in VLSI design. Gain insights into optimization, mapping, and constraint adherence. Read here: https://lnkd.in/gyy5cjUY #VLSI #PhysicalDesign #Synthesis #ChipDesign #Semiconductors #EDA #Electronics #Engineering #Tech #Hardware #Automation #DigitalDesign #IntegratedCircuits #ICDesign #ASIC #FPGA #ElectronicComponents #Technology #Innovation #Learning

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By following a few simple but very effective steps, we can create a complex debug circuit that meets the stringent requirements of modern electronic systems today! While designing a high speed debug circuit, the selection of appropriate high speed debug interface is very critical. The usual debug interfaces like JTAG may not be suitable any more. Considering USB 3.0, PCIe, ethernet interface etc will be the way to go ahead. Bandwidth, latency, protocol overhead computations for each interface is very critical. If multiple (more than 1) clock domains are used , then having proper synchronization circuits like async fifo or handshake protocols are very vital. Using techniques like parallel processing, pipelining, retiming, and clock domain partitioning are equally important to meet timing. We should also allow support for dynamic reconfiguration to quickly adapt to the change in debug requirements. We should also provide enough heat sinks, thermal vias, and airflow to avoid overheating to take care of thermal management. Signal integrity checks must also be performed for high speed debug circuits to ensure there is no reflection , cross talk or signal degradation. 

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Comprehensive guide for VLSI enthusiasts interested in RTL Design along with links of important papers and spec: [1] Digital Electronics: ✓ Good understanding on Combinational, Sequential circuits, FSM and logic gates. ✓ Questions on Skew, Slew, Setup and Hold Window, Metastability, Hold Slack calculation, Synchronizers. Source to learn: ✓ Digital Design by Morris Mano, Digital Design by JF Wakerly, FSM problems from the Digital design book by Charles Roth. [2] Verilog: ✓ Understanding on concepts like continuous assignment, blocking, nonblocking, data types, task/function, delays, data flow and structural modelling style, UDP, Event Queue execution ✓ Coding related to all Combinational and Sequential ckt, sequence detector coding for overlapping and non overlapping FSM (both Mealy and Moore) Sources: ✓ Verilog book by Samir Palnitkar and J bhaskar. ✓ Practice code from edaplayground or open source simulators. [3] SystemVerilog: ✓ First understand the difference b/w Verilog and SV and why do we need SV. ✓ Synthesizable and non Synthesizable constructs. ✓ Concepts of SV interface, arrays, data type like logic, SV event queues. ✓ Re code the same Combinational, Sequential and FSM with SV constructs. Sources: ✓ SV for Design by Stuart Sutherland ✓ 1800.2-2023 SV LRM (focussing the design constraints) [4] IP / Protocol: ✓ All the AMBA protocols like AHB, APB, ATB, AXI, ACE. ✓ Communication protocol like I2C and SPI ✓ Synchronous and Asynchronous FIFO ** Link in comments** [5] Miscellaneous Topics: ✓ Coding guidelines for RTL (Extremely important) ✓ Good understanding on ASIC and FPGA flow. ✓ CDC concepts ✓ Fast and Slow data path calculation ✓ RDC flow and execution #vlsi #asic #semiconductorindustry #electricalengineering

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UP-DOWN COUNTER VERIFICATION Counters are another important component used in today's SoC Understanding how counters work & how to verify them is important. Today we will: 1. Understand the design of an up-down counter 2. Understand various input & output ports 3. Understand how outputs are impacted by inputs 4. Design a testbench to verify the design 5. Give a stimulus to thoroughly test the design 6. Make the stimulus free of compile & run-time errors 7. Analyze the output 8. If there is a bug in the design fix it 9. Rerun the stimulus 10. Ensure design is bug free #rtldesign #rtl #digital #digitalelectronics #digitalelectronics #lectures #computerengineering #computerarchitecture #vlsidesign #vlsi #vlsitraining #vlsijobs #vlsiprojects #verification #verificationengineer #physicaldesign #pd #physicaldesignengineer #semiconductor #semiconductorindustry #career #careerdevelopment #careerguidance #resume #resumebuilding #resumereview #mentor #mentorship #vlsihelpinghands #switispeaks #switipinjani #coding #codinglife #codingtutorial #codingtips #codingjourney #programming #programmer #education #computer #guidance #interview #selfimprovement #selfdevelopment #motivation #careerdevelopment #careers #learning #sv #uvm #systemverilog #soc #ip #asics #cpu #processor #hardwaredescriptionlanguage #cpu #gpu #graphics #supercomputer #tutorial

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Multiple SOC/subsystem verification openings in my team at all experience levels in Noida and Bangalore. interested folks can share / refer CV's to [email protected] while sending your resume, maintain - naming of resume file as " <name>_<domain>_<exp_no>yrs_resume "

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SVA FAQs Ready to test your knowledge on SVA? Let's solve some very interesting questions on SVA. This will test your practical knowledge on SVA when you need to deal with real designs. Ready for the challenge? Link in COMMENT #systemverilog #sv #sva #assertions #verification #vlsi #switispeaks

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What are the reasons for routing congestion 📢 Inefficient floorplan 📢 Macro placement or macro channels is not proper. 📢 Placement blockages not given 📢 No Macro to Macro channel space given. 📢 High cell density 📢 High local utilization 📢 High number of complex cells like AOI/OAI cells which has more pin count are placed together. 📢 Placement of std cells near macros 📢 Logic optimization is not properly done. 📢 Pin density is more on edge of block 📢 Buffers added too many while optimization 📢 IO ports are crisscrossed, it needs to be properly aligned in order. What are the different methods to reduce congestion. 📢 Review the floorplan/macro placements according to the block size and 📢 port placement. 📢 Add proper placement blockages in channels and around the macro boundaries. 📢 Reduce the local density using the percentage utilization/density screens. 📢 Cell padding is applied for high pin density cells, like AOI/OAI. 📢 Check and reorder scan chain if needed. 📢 Run the congestion driven placement with high effort. 📢 Check the power network is proper and on routing tract. If it is not on track, adjacent routing tracts may not be used, so it might lead to congestion

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#100DaysofRTL Day-95 Or construct in SVA Hello all, In SystemVerilog Assertions (SVA), the OR construct is used to assert that at least one of multiple sequences or conditions must hold true. This allows you to check for alternative conditions or events that can satisfy a particular assertion. OR Construct in SVA The OR construct is represented by the or keyword in SVA. It is used to combine multiple sequences or boolean expressions, where the assertion passes if any one of the conditions is true. The OR construct in SVA allows you to assert that at least one of several conditions or sequences must hold true. It's a powerful way to express alternative conditions in your assertions, making it easier to handle complex scenarios where multiple outcomes are acceptable.  👉 check my github repo for the verilog code: https://lnkd.in/gd7UNcFC 👉 Hope you learnt something today #100daysofrtl #intel #verilog #linux #texasinstruments #rtldesign #synopsys #cisco #amd #digital #github #githubactions #github #communication #verilog #systemverilog #verification #intel #synopsys #cadence #nxp #mavensilicon #design #qualcomm #verificationengineer #amd #arm #pentium #vlsi #100codesofrtl #systemverilog #verilogcoding #verilog #rtldesign #designverification #intel #education #passionate #vlsi #vlsipassion #brandambassador #coding #rtlcoding #uvm #vlsidesign #perl #pythonprogramming #100codes #codingchallenge #alsemi #agnisys #greensemi #intel #jntu #studentslife #data #like #start #verificationacademy

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Just a thought RTL Design has few logics which is not required as per the design specifications, this portion of code gets excluded in code coverage analysis. By knowing this fact we still synthesis the logic and it increases the gate counts. but functionaly this logic has no use. Now can this be a area for AI based tool to discard that portion of logic during synthesis and we reduce the gate count?

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