Raju Anand

AXI is a multi channel bus which is popularly used as an interfacing protocol between multiple IP's and is useful both in RTL design and ASIC Verification. Below are the key concepts which are needed to understand AXI protocol in depth. [1] Difference between AXI and AHB. Number of Channels used in AXI. Why there is no separate Read response on AXI. [2] What are out of order and outstanding transaction in AXI. [3] What is the address boundary that slave can access in AXI. [4] Transfer mechanism for Write / Read with / without delay. [5] Valid and Ready hand shaking mechanism. What is deadlock condition. How to overcome it. [6] Difference b/w Incrementing and Wrapping Burst. What is a Fixed Burst type. [7] Difference b/w Bufferable and Cacheable type of transaction in AXI. [8] Complete understanding of Exclusive access phenomenon. Difference b/w OKAY and EXOKAY response. [9] What is a Locked access in AXI3. Why it is removed in AXI4. [10] What are the conditions for SLVERR and DECERR. [11] What is a QOS support for AXI4. What are the significance of AxREGION and AxUSER in AXI4. [12] Difference b/w AXI3 and AXI4. [13] What is a write interleaving method in AXI3 and why it's removed in AXI4. #vlsi #asic #semiconductorindustry #electricalengineering

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Just a thought RTL Design has few logics which is not required as per the design specifications, this portion of code gets excluded in code coverage analysis. By knowing this fact we still synthesis the logic and it increases the gate counts. but functionaly this logic has no use. Now can this be a area for AI based tool to discard that portion of logic during synthesis and we reduce the gate count?

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Recently, Apple has launched the iPhone 16 series, enabling WiFi 7 for iPhone users. Let us do some brief system-level calculations to understand noise and ADC requirements.   Assumptions: Modulation Scheme: 4096-QAM Channel Bandwidth: 320 MHz Received Power (P_RX): -50 dBm Front-end RX Gain ( G ): 25 dB Front-end Noise Figure ( NF ): 10 dB Thermal Noise Power Density ( N_0 ): -174 dBm/Hz Step 1: Thermal Noise Power Calculation The noise power density is a function of thermal noise at room temperature (290K). Given the bandwidth B = 320 MHz, the total noise power over the bandwidth is: N_total = N_0 + 10log10(B) N_total = -174 + 85.05 = -88.95 dBm Step 2: Adjust for Noise Figure by Front End The receiver’s noise figure (NF) adds noise to the system. Adjust the total noise power by the noise figure: N_output = N_total + NF N_output = -88.95 dBm + 10 dB = -78.95 dBm This represents the total noise power at the output of the front end. Step 3: Signal Power at the ADC Input The signal power at the input of the ADC is the received power amplified by the front-end gain (G = 25 dB). P_ADC_in = -50 dBm + 25 dB = -25 dBm Step 4: Signal-to-Noise Ratio (SNR) Calculation The SNR at the ADC is the difference between the signal power at the ADC input and the total noise power at the output: SNR = P_ADC_in – N_output SNR = -25 dBm - (-78.95 dBm) = 53.95 dB This is the SNR at the input of the ADC. Step 5: Determine the ADC Resolution (ENOB) The effective number of bits (ENOB) of the ADC can be determined from the SNR using the relation: SNR = 6.02 x ENOB + 1.76 dB ENOB = (SNR - 1.76) / 6.02 ENOB = (53.95 - 1.76) / 6.02 = 8.67 bits Step 6: Verify SNR Requirement for 4096-QAM For 4096-QAM, the required SNR can be approximated by: SNR_required = 10log10(M), where M = 4096 for 4096-QAM SNR_required = 10log10(4096) = 36 dB Since the calculated SNR at the ADC input (53.95 dB) exceeds the required SNR for 4096-QAM (36 dB), the system is well within the acceptable range for decoding the signal. Step 7: ADC Full-Scale Dynamic Range To ensure proper ADC operation, the full-scale range of the ADC should encompass both the noise floor and the signal power. The total noise power at the ADC input: N_output = -78.95 dBm The signal power at the ADC input: P_ADC_in = -25 dBm Thus, the required dynamic range (difference between the signal and noise) is: Dynamic Range = P_ADC_in – N_output = -25 - (-78.95) = 53.95 dB The ENOB of 8.67 bits corresponds to a dynamic range DR = 6.02 x 8.67 = 52.2 dB This is close to the 53.95 dB SNR at the input of the ADC. Conclusion: For a typical WiFi 7 system with 4096-QAM and 320 MHz bandwidth: Required ADC ENOB: 8.67 bits. However, a nominal ADC resolution of 10 bits would provide adequate performance with design margins for implementation losses, ensuring the system can properly digitize the incoming signal. *Please note that Front End gain is a variable that also plays a crucial role in properly functioning WiFi Receiver.

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📢 Understanding Power, Performance, and Area (PPA) Analysis in VLSI: Key to Efficient Chip Design(Part-2) 🎚 What is the importance of PPA analysis in VLSI ? PPA analysis in VLSI is of paramount importance as it directly impacts the efficiency, functionality, and cost of semiconductor devices. Let's explore in detail why PPA analysis is crucial in VLSI chip design: 📷 Energy Efficiency and Power Consumption: In the era of portable devices and IoT (Internet of Things), energy efficiency is a critical consideration. PPA analysis helps identify power-hungry sections in the chip, allowing designers to implement power optimization techniques such as clock gating, power gating, and dynamic voltage scaling. By reducing power consumption during idle or low-activity states, PPA analysis extends battery life and ensures the device operates with minimal energy wastage. 📷Performance Optimization: Performance is a key factor in determining the effectiveness of a VLSI chip. PPA analysis helps identify bottlenecks, potential timing violations, and areas where performance can be enhanced. By optimizing the design for maximum performance, chip manufacturers can meet or exceed user expectations for computation speed and responsiveness. 📷 Area Minimization and Cost Reduction: Area reduction directly impacts the cost of manufacturing VLSI chips. Smaller chips allow for more chips to be fabricated on a single wafer, leading to higher yield and lower production costs. PPA analysis assists in identifying opportunities for layout optimization, better floor planning, and efficient use of silicon real estate, resulting in cost-effective chip designs. 📷 Yield Improvement and Quality Assurance: PPA analysis aids in detecting potential design flaws early in the chip design process. By identifying and addressing issues related to power, performance, and area, designers can improve chip yield and overall reliability. This reduces the risk of costly chip re-spins and ensures a smoother production process. 📷 Trade-Off Analysis: PPA analysis helps in understanding the trade-offs between power, performance, and area. Designers can evaluate different design choices and architectural trade-offs to strike the optimal balance based on the application requirements. For instance, in mobile devices, the emphasis might be on power efficiency, whereas in high-performance computing applications, the focus could be on maximizing computational speed. 📷 Time-to-Market Acceleration: Efficient PPA analysis allows designers to quickly identify potential issues and make informed design decisions. By resolving issues early in the design process, time-consuming iterations and design iterations are minimized, leading to faster time-to-market for new chips and products.

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Technical job!! Technical Questionnaire proficiency Hardware 1. Function of SMPS does in computer?(Basic) 2. What is a firmware? (Basic) 3. Share different types of hard drives (HDD/SSD) (Basic) 4. What is the difference between RAM and ROM(Basic) 5. What is CMOS ? (Basic) 6. Latest type of router available in the market(Basic) 7. Difference between USB 2.0 and USB 3.0(Basic) Device Drivers 8. What are device drivers (Basic) 9. From where can you install drivers on PC? (Basic) 10. How to update device drivers ? (Basic) Windows Operating System 11. Different types of Operating system. (Basic) 12. Function of Operating system(Basic) 13. What is a role of device manager(Intermediate) 14. Function of BIOS(Intermediate) 15. Command to verify the version of Windows on a desktop/laptop(Basic) 16. How do you find a version of OS on windows 10 PC? (Basic) 17. What is POST process (Intermediate) 18. Command for device manager(Intermediate) 19. How can you uninstall or remove software from your computer? (Basic) 20. How can you get into BIOS? (Basic) 21. How many bits makes one byte(Basic) 22. From where does your CPU gets power from? (Basic) 23. What is LKGC?(Intermediate) 24. What is Safe mode .How do you get into Safe mode and what are the different options under Safe mode(intermediate) 25. Situation based questions ( for example when you shut down your laptop it shows the correct time and when you open the laptop it continues to show the correct time , how does that happen ? )(Intermediate) 26. How do you perform system restore ?(Intermediate)) 27. What is system configuration utility (MSCONFIG)( (Intermediate) 28. How do you upgrade from Windows 7 to Windows 10 (Expert) 29. Difference between System Reset and System Restore ?( (Intermediate) 30. What does boot manager do ? (Expert) 31. What is boot configuration data ?(Expert) 32. What is LKGC ?(Intermediate) 33. How to uninstall programs in windows 8(Basic) 34. What is kernel ?(Intermediate) 35. Storage space on DVD(Basic) 36. What is device manager? (Basic) 37. What is memory cache n its function(Intermediate) 38. Shortcut for System restore(Intermediate) 39. What is WPA(Basic) Troubleshooting issues 1. How do you troubleshoot issue with NO BOOT(Expert) 2. How do you troubleshoot issue with NO POST(Expert) 3. How do you troubleshoot issue with NO Power(Expert) 4. How do you troubleshoot issue with NO Display(Expert) 5. How do you troubleshoot issue with Page cannot be displayed(for both secure and unsecured websites) (Expert) 6. If in case you start up your computer and uh can only hear beep sound how will you fix it? (Expert) 7. What is a Blue Screen Error & how to troubleshoot that ? (Expert) 8. What is a black screen issue & how to troubleshoot that ? (Expert) 9. How to troubleshoot issue with Windows update getting stuck in between download(Expert) 10. How do your troubleshoot when your device manager comes up as blank(Expert) 11. How to fix slow boot issue windows 8/Windows

What are the reasons for routing congestion 📢 Inefficient floorplan 📢 Macro placement or macro channels is not proper. 📢 Placement blockages not given 📢 No Macro to Macro channel space given. 📢 High cell density 📢 High local utilization 📢 High number of complex cells like AOI/OAI cells which has more pin count are placed together. 📢 Placement of std cells near macros 📢 Logic optimization is not properly done. 📢 Pin density is more on edge of block 📢 Buffers added too many while optimization 📢 IO ports are crisscrossed, it needs to be properly aligned in order. What are the different methods to reduce congestion. 📢 Review the floorplan/macro placements according to the block size and 📢 port placement. 📢 Add proper placement blockages in channels and around the macro boundaries. 📢 Reduce the local density using the percentage utilization/density screens. 📢 Cell padding is applied for high pin density cells, like AOI/OAI. 📢 Check and reorder scan chain if needed. 📢 Run the congestion driven placement with high effort. 📢 Check the power network is proper and on routing tract. If it is not on track, adjacent routing tracts may not be used, so it might lead to congestion

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Key and basic concepts of UVM which are very important and need to be understood by someone who wants to enter into the domain of ASIC Verification in VLSI: [1] UVM Phasing Mechanism and how it executes. What is the role of reset, configure, main and shutdown phase of run phase. [2] Which Phases are categorised into task and function. Which Phases are divided into top down and bottom up approach. [3] Conditions and need to introduce domain Synchronisation and Phase jumping in UVM Phasing Mechanism. [4] Role of run_test in top module and its importance. Why UVM is called a DAC and role of uvm_root. [5] Difference b/w physical and Virtual interface. How VIF actually works in UVM and how it flows in testbench hierarchy. [6] Generic role of UVC's like Driver, Monitor, Scoreboard, etc. [7] What is Configuration in UVM. Difference b/w uvm_config_db and uvm_resource_db. [8] Sequencer to Driver handshaking mechanism flow for unidirectional, Bidirectional and Pipelined transfer. [9] Difference between uvm_component, uvm_object and uvm_transaction. What will happen if we don't use component and object utils macro. [10] What is Factory registration in UVM. Concept of factory override and it's different type. [11] Difference between TLM port and analysis port. Difference between port, export and imp. What are hierarchical exports. [12] Objection mechanism in UVM and importance raise and drop objection. [13] Sequence item flow and how to start a test / sequence. How to create a library of sequence. [14] Why Driver run phase uses only nonblocking assignment and not blocking. [15] How UVM handle race conditions and detect them. All the concepts can not be covered in a single post, I will create another post with intermediate concepts. #vlsi #asic #semiconductorindustry #electricalengineering

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📢 Understanding Power, Performance, and Area (PPA) Analysis in VLSI: Key to Efficient Chip Design(Part-4) 🎯What are the methodologies for PPA analysis in VLSI ? PPA analysis in VLSI involves a set of methodologies and techniques to optimize the power consumption, performance, and chip area of semiconductor devices. Here are the key methodologies used for PPA analysis in VLSI: 🎯Architectural Exploration: Architectural exploration is a crucial initial step in P PA analysis. It involves studying various chip architectures and design alternatives at the conceptual level to identify the most suitable trade-offs between power, performance, and area. Designers assess different architectural choices, such as pipelining, parallel processing, memory hierarchy, and cache sizes, to understand their impact on PPA metrics. The goal is to find an optimal architecture that meets the target performance while adhering to power and area constraints. 🎯 Power Estimation: Power estimation involves modeling and predicting the power consumption of a VLSI chip at different operational states and scenarios. Power estimation can be performed at various levels of abstraction, including gate level, RTL, and system level. Power estimation tools help designers identify power-hungry sections or modules within the chip. Understanding power consumption patterns aids in the implementation of targeted power optimization techniques, such as clock gating, power gating, and voltage scaling. 🎯 Performance Modeling: Performance modeling is used to predict the chip's performance under various workloads, clock frequencies, and environmental conditions. Simulation tools are employed to analyze critical paths, timing constraints, and potential bottlenecks that may limit the chip's maximum achievable performance. By understanding the chip's performance characteristics, designers can make informed decisions to optimize performance, ensuring that the chip operates at its full potential. 🎯Area Optimization: Area optimization focuses on reducing the physical footprint of the chip. It involves various design methodologies, such as layout synthesis, floorplanning, and logic synthesis, to achieve efficient use of silicon real estate. By minimizing the chip's area, more chips can be fabricated on a single wafer, leading to higher yield and reduced manufacturing costs. Area optimization also enables the integration of more functionalities on a chip without compromising on power and performance.

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Dear Chip Designers, . . . In the fast faced Semiconductor Industry, A Strong Individuals can Resolve Perceived Weaknesses in Teams. A New hire team lead can make or break the entire team, I have seen this multiple times. In the dynamic landscape of the Semiconductor industry, success often hinges on the collective strength of teams. However, even the most skilled teams may face challenges when dealing with perceived weaknesses among members. In this, lets delve into the transformative power of strong individuals in resolving these issues, ultimately fostering a culture of collaboration, innovation, and success. Identifying Perceived Weaknesses: Before delving into solutions, it's crucial to identify the perceived weaknesses that may hinder team performance. These can range from lack of technical proficiency to communication barriers or even interpersonal conflicts. The Role of Strong Individuals: Strong individuals possess a unique set of qualities that can significantly impact team dynamics. These individuals are not only technically proficient but also exhibit strong leadership, communication, and problem-solving skills. Their presence within teams can serve as a catalyst for positive change, bridging gaps and inspiring others to elevate their performance. Key Solutions and Strategies: Lead by Example: Strong individuals lead not only through their words but also through their actions. By setting high standards and demonstrating commitment to excellence, they inspire others to follow suit. Facilitate Open Communication: Effective communication is the cornerstone of successful teams. Strong individuals actively foster an environment where team members feel comfortable expressing their ideas, concerns, and feedback. Offer Mentorship and Support: Strong individuals recognize the importance of nurturing talent within the team. They willingly share their knowledge and experiences, empowering others to grow and develop their skills. Address Conflict Constructively: Conflict is inevitable within any team, but strong individuals approach it as an opportunity for growth rather than a hindrance. They facilitate constructive discussions and work towards finding mutually beneficial solutions. Celebrate Diversity: Strong individuals appreciate the value of diversity in perspectives and backgrounds. They actively seek out input from all team members, recognizing that innovation thrives in an inclusive environment. Case Studies and Success Stories: To illustrate the effectiveness of leveraging strong individuals within teams, we present real-life case studies from leading semiconductor companies. These stories highlight how the presence of strong individuals has transformed teams, overcoming challenges and achieving remarkable results. As we move forward, let us recognize and empower these individuals to drive positive change and propel our industry towards new heights. #semiconductor #Semiconductors #Chip #VLSI

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How to understand UVM Testbench in detail needed in ASIC Verification in VLSI: There are multiple components and objects which build the UVM testbench hierarchy. Among them, one important block is Agent which has three components Sequencer, Driver and Monitor. Below concepts are useful in learning the structure in detail: ✓ Sequencer <--> Driver handshaking mechanism for a. Only for req Id. b. Both req and RSP c. Pipelined and Non Pipelined access d. Wait States ✓ Use of Non blocking assignment in Driver logic code why? ✓ How to use clockvar in Driver. ✓ Configuration mechanism in Driver. Can we use UVM resource db. ✓ Factory registration and factory override. ✓ Use of function new() ✓ How to start a sequence item and randomize. ✓ How to handle multiple sequence item through Sequencer --> Use of arbitration algorithm. ✓ How to handle interrupts ✓ What is user arbitration and need of it ✓ Use of analysis port and TLM port. How to connect analysis port to subscribers. ✓ Different types of Port export connection. ✓ Use of p / m sequencer. ✓ How write function needs to be implemented. ✓ Difference b/w active and passive agent. ✓ Why Monitor uses new() instead of create method. ✓ Difference b/w TLM1.0 and TLM2.0 #vlsi #asic #electronics #electricalengineering

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𝑾𝒉𝒚 𝑺𝑻𝑴32 𝒆𝒗𝒂𝒍𝒖𝒂𝒕𝒊𝒐𝒏 𝒃𝒐𝒂𝒓𝒅 ?  I have a range of evaluation boards from all well known semiconductor companies including NxP , ST, Nuvoton, TI , Microchip, Broadcom, Nordic, NVIDIA etc. That was part of my investment. I got loaner boards from ST, NxP and Nuvoton. I used following parameters to decide evaluation board : 1: 𝘾𝙤𝙢𝙥𝙖𝙣𝙮 𝙝𝙞𝙨𝙩𝙤𝙧𝙮 I have used ST devices around 1998 as well. 2: 𝙍𝙤𝙖𝙙𝙢𝙖𝙥 : They have a range of products in various domains 3: 𝘾𝙤𝙨𝙩: It is most important factor and their boards are available in Arduino range as well. 4: 𝙀𝙘𝙤𝙨𝙮𝙨𝙩𝙚𝙢 : They have a variety of tools for Pin multiplexing, Flash programming, Debugging and even for AI. 5: 𝙎𝙪𝙥𝙥𝙤𝙧𝙩 :  I never had issue in contacting ST Marketing , Development , FAE and distributor FAEs . In fact , now my student is also supporting ST devices in India. I was invited for a combined session with faculty as well. 6: 𝙅𝙤𝙗 𝙤𝙥𝙥𝙤𝙧𝙩𝙪𝙣𝙞𝙩𝙞𝙚𝙨 : Since STM32 is based on ARM and being widely used in India. It increases your possibility to get job. Here is outcome of my experience with ST device. This week was little bit interesting in embedded system live sessions. 1: Enabled one US based student in the STM32 evaluation board which I never used. It was done in live session. We supported multiple devices in past but it was instant support over live session. 2: Yesterday also another US based student shared board over camera. We started with default HAL project to do sanity check. First surprise was warning " Obsolete board" . We ignored and continued . Next surprise was "Insufficient flash memory" even with default configuration. This was because it had enabled all peripherals. I asked student to put while(1); in the beginning. Linker was kind enough to discard all other code and we could reach at main() at least. This was simple but important for student to move ahead. Both above students are working professionals in US and joined Embedkari for a refresh cycle. For joining Embedkari, no shubh muhurt is required because every moment is part of God's creation 😀 ... Join anytime . and #salarybadhao #microcontroller #microcontrollers #embedded #embeddedsystem #embeddedlinux #embeddedc #freertos #firmware #firmwareengineer #firmwarejobs #devicedriver #softwareengineers #electronics #embeddedjobs #embeddedsystems #embeddedengineer #embedkari #opentowork #freshers #stm32

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Comprehensive guide for VLSI enthusiasts interested in RTL Design along with links of important papers and spec: [1] Digital Electronics: ✓ Good understanding on Combinational, Sequential circuits, FSM and logic gates. ✓ Questions on Skew, Slew, Setup and Hold Window, Metastability, Hold Slack calculation, Synchronizers. Source to learn: ✓ Digital Design by Morris Mano, Digital Design by JF Wakerly, FSM problems from the Digital design book by Charles Roth. [2] Verilog: ✓ Understanding on concepts like continuous assignment, blocking, nonblocking, data types, task/function, delays, data flow and structural modelling style, UDP, Event Queue execution ✓ Coding related to all Combinational and Sequential ckt, sequence detector coding for overlapping and non overlapping FSM (both Mealy and Moore) Sources: ✓ Verilog book by Samir Palnitkar and J bhaskar. ✓ Practice code from edaplayground or open source simulators. [3] SystemVerilog: ✓ First understand the difference b/w Verilog and SV and why do we need SV. ✓ Synthesizable and non Synthesizable constructs. ✓ Concepts of SV interface, arrays, data type like logic, SV event queues. ✓ Re code the same Combinational, Sequential and FSM with SV constructs. Sources: ✓ SV for Design by Stuart Sutherland ✓ 1800.2-2023 SV LRM (focussing the design constraints) [4] IP / Protocol: ✓ All the AMBA protocols like AHB, APB, ATB, AXI, ACE. ✓ Communication protocol like I2C and SPI ✓ Synchronous and Asynchronous FIFO ** Link in comments** [5] Miscellaneous Topics: ✓ Coding guidelines for RTL (Extremely important) ✓ Good understanding on ASIC and FPGA flow. ✓ CDC concepts ✓ Fast and Slow data path calculation ✓ RDC flow and execution #vlsi #asic #semiconductorindustry #electricalengineering

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Common Resource Block (CRB) in 5G-NR 1. CRBs are set of RBs which occupy channel bandwidth and they are defined for each subcarrier spacing. 2. CRBs provide the RB numbering throughout the carrier bandwidth while PRBs provide RB numbering within each BWP. 3. They are numbered from 0 in upward direction where CRB 0 is located at lower side of Channel Bandwidth. 4. The CRBs associated with each and every SCS are aligned at Point A  i.e., the center of subcarrier 0 of CRB 0 for each subcarrier spacing coincides with Point A. 5. From figure, the CRB edges for different SCS are not aligned. The CRB edge with SCS = 2∆f is shifted by ∆f kHz as compared to CRB edge with SCS= ∆f. For example, the CRB edge with SCS= 30kHz is shifted by 7.5kHz as compared to CRB edge with SCS= 15kHz. 6. UE determines the position of 'Point A' using ARFCN provided by SIB1 or dedicated signalling from gNB. SIB1 provides the FrequencyInfoDL-SIB parameter including IE "offset to carrier value" specifying the number of RBs between 'Point A' and subcarrier 0 and also IE 'carrierBandwidth' that specifics the number of RBs which are available.  #5g #5gnetwork #5gnr #communication #5gtechnology

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📢 Understanding Power, Performance, and Area (PPA) Analysis in VLSI: Key to Efficient Chip Design(Part-1) 🔋 Understanding Power, Performance, and Area (PPA): Power: Power consumption is a key concern in today's electronic devices. Lower power consumption translates to longer battery life, reduced heat dissipation, and enhanced environmental sustainability. PPA analysis assesses power usage at various stages of chip operation - from idle states to peak performance - to ensure efficient power management. 🔌 Performance: Performance, often measured in terms of clock frequency or execution speed, determines how quickly a chip can process instructions and deliver results. A higher-performing chip enables faster computation and improved user experience. PPA analysis aims to achieve the highest performance possible while adhering to power and area constraints. 🔋 Area: The area of a chip refers to the physical space it occupies on the silicon die. Smaller chips allow for higher packing densities, leading to cost savings and increased functionality. PPA analysis strives to minimize the chip's physical footprint while maintaining desired power and performance characteristics.

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#Micron, #Hyderbad is looking #Mtech Freshers from Premium colleges. and Good exposure on #Python #semiconductor Knowledge #EDA Tools #Verilog #CMOS #UART #TCAD Share your Updated CV to [email protected] Connect with Our Hiring Team: Narayanan Ramanan Gopi Krishna Vemuri Rajesh Kumar Gupta Seema Kharayat Shrashti Sai . Revathi P #Mtech #Freshers #IIT #NIT #Mirconhiring #Hyderbad #Python #Scripting

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How Artificial Intelligence is going to improve chip design? Artificial intelligence is going to enter in almost every sector wherever job can be automated. VLSI chip design is also going to be benefitted by using AI. Already many companies have started using AI in their tools. Some key points about AI in VLSI AI Applications in VLSI: 1. Design Automation: AI optimizes chip design, reducing manual effort and increasing productivity. 2. Layout Optimization: AI algorithms optimize chip layout for better performance, power consumption, and area utilization. 3. Verification and Validation: AI-powered tools detect bugs and errors, ensuring high-quality chip designs. 4. Manufacturing Yield Prediction: AI predicts manufacturing yield, enabling proactive defect reduction. 5. Test Pattern Generation: AI generates efficient test patterns, reducing testing time and costs. 6. Chip Performance Optimization: AI optimizes chip performance, power consumption, and thermal management. AI Techniques Used: 1. Machine Learning (ML): ML algorithms learn from data to improve design and manufacturing processes. 2. Deep Learning (DL): DL techniques, like neural networks, analyze complex design and manufacturing data. 3. Natural Language Processing (NLP): NLP enables human-AI collaboration and design documentation analysis. 4. Computer Vision: Computer vision techniques inspect and analyze chip designs and manufacturing data. Benefits: 1. Increased Efficiency: AI automates repetitive tasks, freeing engineers for high-value tasks. 2. Improved Quality: AI detects errors and optimizes designs, ensuring high-quality chips. 3. Reduced Time-to-Market: AI accelerates design and manufacturing processes. 4. Cost Savings: AI reduces design and manufacturing costs. Challenges on the way: 1. Data Quality: AI requires high-quality, relevant data for effective learning. 2. Interoperability: Integrating AI tools with existing design and manufacturing systems. 3. Security: Ensuring AI-driven design and manufacturing processes are secure. And more importantly the main thing about adoption of AI is trust on the entire process. what do you think which direction AI would go in chip design? #vlsi #chip #design #Artificial #intelligence

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Lakhs of Base DRC at Floorplan / Placement database | Physical Verification | Interview Question: Let's say you are working on one of the complex blocks of chip designing and you are responsible for closing the Place-and-Route (PnR) activity of the design. You are responsible for doing floor-planning, placement, clock tree synthesis, routing, and signoff activities. Floorplan is one of the most important tasks in physical design activities. One of the major tasks in floor-planning is macro placement, identification, and creation of physical power domains based on UPF, doing power planning including placement of physical cells like tap cells, boundary cells, power switches, guard rings, marker cells, and a few others. Read more @https://lnkd.in/guAgJySy Happy Learning! #scripting #coding #Tcl #pd #physicaldesign #physicalverification #pv #vlsi #design #india #semiconductor #freshers #professional #hardware #floorplanning #motivation #leadership #magnet #bound #placement #synopsys #cadence #interview #vlsi #question #longer #routing #longnet #delay #timing #rc #resistance #capacitance #basedrc #intel #infineon #nvidia #amd #interview #freshers

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Unlock Your Potential: 10 Tips to Grow as a VLSI Engineer As a VLSI Engineer, you're part of a highly specialized field that's driving technological innovation. To stay ahead, continuous learning and growth are crucial. Here are 10 tips to help you advance your career: 1. Stay Current with Industry Trends Follow industry leaders, researchers, and publications to stay updated on: - Emerging technologies (AI, IoT, 5G) - New design methodologies (FinFET, 3D IC) - Advancements in EDA tools (Synopsys, Cadence) 2. Develop a Strong Foundation in Digital Design Master: - Verilog/VHDL - Digital logic design - Microarchitecture - FPGA design 3. Expand Your Skill Set to Analog and Mixed-Signal Design Learn: - Analog circuit design - Mixed-signal design - ASIC design - Physical design 4. Familiarize Yourself with EDA Tools Proficiently use: - Synopsys (VCS, Design Compiler) - Cadence (Innovus, Virtuoso) - Mentor Graphics (ModelSim, Questa) 5. Participate in Projects and Competitions Join: - VLSI design contests - Hackathons - Open-source projects - Research initiatives 6. Network with Peers and Industry Experts Attend: - Conferences (DAC, ICCAD) - Workshops - Webinars - Online forums (Reddit, LinkedIn groups) 7. Pursue Higher Education and Certifications Consider: - Master's or Ph.D. in VLSI or related fields - Certifications (VLSI Design, ASIC Design) 8. Stay Up-to-Date with Industry Standards Familiarize yourself with: - IEEE standards (1801, 1076) - IPC standards (J-STD-020) 9. Develop Soft Skills Improve: - Communication - Teamwork - Time management - Leadership 10. Join Online Communities and Forums Engage with: - VLSI subreddit - VLSI professionals on LinkedIn - Online forums (EDABoard, VLSI Forum) Take Your Career to the Next Level! By following these tips, you'll enhance your skills, stay industry-relevant, and advance your VLSI engineering career. Share Your Thoughts! #VLSI #Semiconductor #Engineering #CareerDevelopment #IndustryTrends #Innovation #Technology Bala Gorthi Rekha P Jyothi G Rushang shah Eximietas Design BinduLatha D

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Indian semiconductor ecosystem is thriving. With big push from government, an excellent corporate-govt partnership and an awakened indian market who is valuing “make in India , made for India , made by Indians” movement. A great energy and synergy everywhere. Follow VLSI Society of India (VSI)

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