Prof. Mayank Shrivastava

𝑾𝒉𝒚 𝑺𝑻𝑴32 𝒆𝒗𝒂𝒍𝒖𝒂𝒕𝒊𝒐𝒏 𝒃𝒐𝒂𝒓𝒅 ?  I have a range of evaluation boards from all well known semiconductor companies including NxP , ST, Nuvoton, TI , Microchip, Broadcom, Nordic, NVIDIA etc. That was part of my investment. I got loaner boards from ST, NxP and Nuvoton. I used following parameters to decide evaluation board : 1: 𝘾𝙤𝙢𝙥𝙖𝙣𝙮 𝙝𝙞𝙨𝙩𝙤𝙧𝙮 I have used ST devices around 1998 as well. 2: 𝙍𝙤𝙖𝙙𝙢𝙖𝙥 : They have a range of products in various domains 3: 𝘾𝙤𝙨𝙩: It is most important factor and their boards are available in Arduino range as well. 4: 𝙀𝙘𝙤𝙨𝙮𝙨𝙩𝙚𝙢 : They have a variety of tools for Pin multiplexing, Flash programming, Debugging and even for AI. 5: 𝙎𝙪𝙥𝙥𝙤𝙧𝙩 :  I never had issue in contacting ST Marketing , Development , FAE and distributor FAEs . In fact , now my student is also supporting ST devices in India. I was invited for a combined session with faculty as well. 6: 𝙅𝙤𝙗 𝙤𝙥𝙥𝙤𝙧𝙩𝙪𝙣𝙞𝙩𝙞𝙚𝙨 : Since STM32 is based on ARM and being widely used in India. It increases your possibility to get job. Here is outcome of my experience with ST device. This week was little bit interesting in embedded system live sessions. 1: Enabled one US based student in the STM32 evaluation board which I never used. It was done in live session. We supported multiple devices in past but it was instant support over live session. 2: Yesterday also another US based student shared board over camera. We started with default HAL project to do sanity check. First surprise was warning " Obsolete board" . We ignored and continued . Next surprise was "Insufficient flash memory" even with default configuration. This was because it had enabled all peripherals. I asked student to put while(1); in the beginning. Linker was kind enough to discard all other code and we could reach at main() at least. This was simple but important for student to move ahead. Both above students are working professionals in US and joined Embedkari for a refresh cycle. For joining Embedkari, no shubh muhurt is required because every moment is part of God's creation 😀 ... Join anytime . and #salarybadhao #microcontroller #microcontrollers #embedded #embeddedsystem #embeddedlinux #embeddedc #freertos #firmware #firmwareengineer #firmwarejobs #devicedriver #softwareengineers #electronics #embeddedjobs #embeddedsystems #embeddedengineer #embedkari #opentowork #freshers #stm32

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**Unlock Your VLSI Potential: Semicon Technolabs Live Demo on Analog Layout – Nov 10th, 2024 at 10 AM IST** The VLSI industry is growing at an unprecedented pace, but there's a significant gap in the availability of skilled professionals to meet the demand for cutting-edge semiconductor technologies. To help bridge this gap, **Semicon Technolabs** is hosting a **live demo on Analog Layout**a crucial skill in the VLSI design process on **November 10th, 2024**, at **10:00 AM IST**. This live demo is designed to provide students, recent graduates, and professionals with the hands-on knowledge they need to excel in the world of analog IC design. Whether you’re looking to get into the VLSI industry or expand your skillset, this session will provide you with a deeper understanding of analog layout design techniques and how to apply them in real-world scenarios. **What You’ll Learn in the Live Demo:** - **Introduction to Analog Layout**: Gain a foundational understanding of analog IC design and the importance of layout in the VLSI process. - **Key Concepts and Techniques**: Explore critical analog layout techniques such as transistor sizing, device matching, and parasitic extraction. - **Tools of the Trade**: Get exposure to industry-standard EDA tools used in analog layout design. - **Practical Tips & Best Practices**: Learn how to optimize layouts for PPA while adhering to design rules. - **Career Opportunities in Analog Layout**: Understand how mastering analog layout can help you stand out in the competitive job market. **Why Should You Enroll?** 1. **Bridging the Industry Skill Gap**: The VLSI sector is booming, but there's a significant shortage of skilled professionals in specialized areas like analog layout. This demo will equip you to understand the industry needs. 2. **Practical Learning**: Unlike typical classroom sessions, this demo will focus on practical techniques that you can apply to real-world design challenges. Learn by doing, not just by listening. 3. **Interactive Q&A with Experts**: After the demo, there will be an opportunity for you to ask questions directly to the experts at Semicon Technolabs. Get valuable insights into the industry and get answers to your specific queries. 4. **Kickstart Your VLSI Career**: If you are a student or recent graduate, this is a great way to make yourself more marketable to employers in the rapidly growing semiconductor industry. **Conclusion:** Semicon Technolabs is offering an invaluable opportunity for anyone looking to break into the VLSI industry. Analog layout design is a key area of expertise, and mastering it could be the key to unlocking numerous career opportunities. Registration Form- https://lnkd.in/efJSrE8K Subscribe to Our YouTube Channel- https://lnkd.in/e6Ka_j_y #FreeDemo #DEMO2024 #SemiconTraining #engineeringcareers #EngineeringGraduates #Graduates #graduates2024 #vlsi #vlsidesign #techfuture #CareerInTech #BTech #MTechGraduates

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Let’s build companies that matter

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*Key Takeaways from SEMICON India 2024* *1. Visionary Goal* Honorable PM's ultimate aim: "Made in Bharat" chips in every electronic system globally. *2. Strategic Approach* Path to success: - System Engineering Approach - Conducive ecosystem - Trust in partnerships - Collaboration with international partners and established players *3. Government Support* Government of India's commitment: - Open and unconditional support - Clear vision and roadmap - Emphasis on self-sustainability *4. R&D and Innovation* Establishing Bharat Semiconductor Research Centre (BSRC): - Technology/IP development - Silicon validation *5. Critical Success Factor* Avoid single-point failure: - Foster teamwork and collaboration - Adopt parallel approaches to mitigate risks These conclusions highlight India's ambitious plans to become a significant player in the global semiconductor industry, leveraging a collaborative and innovative approach.

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*Key Takeaways from SEMICON India 2024* *1. Visionary Goal* Honorable PM's ultimate aim: "Made in Bharat" chips in every electronic system globally. *2. Strategic Approach* Path to success: - System Engineering Approach - Conducive ecosystem - Trust in partnerships - Collaboration with international partners and established players *3. Government Support* Government of India's commitment: - Open and unconditional support - Clear vision and roadmap - Emphasis on self-sustainability *4. R&D and Innovation* Establishing Bharat Semiconductor Research Centre (BSRC): - Technology/IP development - Silicon validation *5. Critical Success Factor* Avoid single-point failure: - Foster teamwork and collaboration - Adopt parallel approaches to mitigate risks These conclusions highlight India's ambitious plans to become a significant player in the global semiconductor industry, leveraging a collaborative and innovative approach.

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Walking down memory lane.... (Fabrication and characterization of MOSFET).. What is the normal and abnormal behaviour of a n-channel MOSFET? In the world of semiconductor devices, n-channel Metal-Oxide-Semiconductor Field-Effect Transistors (n-MOSFETs) are crucial components in modern electronics, from power management circuits to digital logic. Check it out experimental characterization of an n-channel MOSFET 😄 . #MOSFET #Semiconductors #nMOSFET #Characterization #Electronics #Engineering #TechInnovation #CircuitDesign #industry #physics

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CPU Micro-architect and RTL Design Location: Bangalore More about us: We are a well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original RISC architecture, our processors have shipped into billions of consumer and enterprise products. Seeking experienced Micro-architect and RTL engineers to own and lead RTL development of one or more modules of a high-performance CPU core. Working knowledge of the pipeline stages of an in-order or out-of-order high performance CPU core is necessary. Candidate will be responsible for all aspects of the design including Performance, Power, and Area. Minimum Qualifications MS degree in Electrical or Computer Engineering with 5+ years or BS degree with 7+ years of practical experience Through knowledge of microprocessor architecture including expertise in one or more of the following areas: Instruction fetch and decode, branch prediction Instruction scheduling and register renaming Out-of-order execution Integer and Floating-point execution Load/Store execution, prefetching Cache and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Preferred Qualifications Experience with designing RISC-V, ARM and/or MIPS CPU Experience with Hardware multi-threading, virtualization, and SIMD designs Understanding of high-performance techniques and trade-offs in a CPU microarchitecture Understanding of low power microarchitecture techniques Experience using a scripting language such as Perl or Python Roles and Responsibilities Drive the micro-architecture and design of a critical CPU block or multiple blocks of a CPU core Performance exploration - explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification - From early high-level architectural exploration, through micro architectural research and arriving at detailed specification. RTL ownership - Configurable Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals Functional verification support - help the design verification team execute the functional verification strategy. Performance verification support - help verify that the RTL design meets the performance goals. Design delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power. #rtldesign #riscv #arm #vector #vsu #fabric #interconnect #cpuarchitecture #microarchitecture #simd #mips #verilog #cache #architecture Contact: Uday Mulya Technologies [email protected] "Mining The Knowledge Community"

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✅ CMOS, FinFET, GAAFET, and Emerging Transistor Technologies ✅ Most recommended for Undergraduates and VLSI Aspirants, do follow for daily updates Outline • What is Moore’s Law • Nano-Meter Technology • CMOS Technology • FinFET Technology • GAAFET Technology 👉 👉 Please do follow & do share 👉 👉 For more information do follow ProV Logic or Prasanthi Chanda

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I am looking for some answers and insight. Is there any difference in data, image quality and time for acquisition when we are comparing CMOS and Phosphor Screen based EBSD detectors over the newly developed DeD semiconductor based EBSD detectors ? #EBSD #FAILUREANALYSIS #ELECTRONMICROSCOPY #MICROSTRUCTURE #TEXTURE #materialsscience #material #SEM #EBSP

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Making reliable electrical contact to 2D semiconductors remains a major challenge in creating high-performance nanoscale transistors. While much attention is rightfully paid to factors like work function, band alignment, and mid-gap states, the role of mechanical strain is often overlooked. In our latest paper, led by PhD student Lauren Hoang (co-advised with Prof. Eric Pop), we highlight how contact-induced strain from Ni electrical contacts significantly influences the performance of monolayer WS2 transistors. The fact that Ni has historically performed well as an electrode for WS2 seemed strange to us because -- in theory -- the workfunction should be slightly worse than gold for good n-type contact to WS2. We were particularly surprised to find that 1 μm-wide Ni contacts led to significantly better charge transport than 0.1 μm-wide contacts. Lauren investigated carefully and determined that the devices with 1 µm Ni contacts were under substantial uniaxial tensile strain (~0.7%). We found that longer Ni contacts (1 μm) lead to a 78% reduction in contact resistance compared to shorter contacts (0.1 µm). Additionally, the longer contacts resulted in a 2.67× improvement in on-current for short-channel devices (Lch = 100 nm) and a 1.35× improvement for long-channel devices (Lch = 1 μm). The peak transconductance also saw a 1.74× increase in long-channel devices with longer contacts. Aided by key strain processing insights by Marc Jaikissoon and modeling from Cagil Koroglu (FEA) and Robert Bennett (DFT), we were able to confirm the strain and rationalize our observations (all made possible by excellent material from Zhepeng Zhang). Interestingly, we also discovered that thermal annealing can relax the strain, resulting in decreased transistor performance. However, with careful engineering such as dielectric encapsulation, the strain-induced performance boost can be preserved following annealing. Congrats, Lauren and Team, for the great work! (Published in ACS Publications Nano Letters)

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I got in touch with Prof. V Ramgopal Rao from Birla Institute of Technology and Science, Pilani to understand India's semiconductor mission. The Indian government has been very clear and focussed about its semiconductor mission, which was launched in 2021. Currently, India is the second largest importer of semiconductor chips globally after a 92% increase in chip imports in the last three years. “Given our infrastructure and the lack of ecosystem for semiconductor supplies, companies hesitate to venture into this field in India. A semiconductor foundry also requires many auxiliary industries such as semiconductor grade gases and chemical supplies, which are not present in India," he said. Though there are a number of designing and manufacturing companies in India, there is no foundry. Despite several semiconductor startups present in Bengaluru, manufacturing still happens in other countries. The present government is making significant efforts to woo the semiconductor players with massive subsidies. These subsidies can easily go to over 50%. Increasing interest from semiconductor companies and joint partnerships with Indian companies may eventually help India achieve its target of capturing 10% of the world’s semiconductor market by 2030. “For design, India is already a global powerhouse”. he said. He also believes that the reason India hasn’t built something like a Tesla is because of a lack of collaboration with academia. Despite a thriving automotive industry, “Nobody wants to take mechanical engineering or study other automotive subjects in the country because there aren’t any decent paying jobs. This is a result of lack of innovation and lack of collaborations between industry and academia." “It took OpenAI tens of billions of dollars to make ChatGPT. The research funding in India is so tiny,” he added. For AI, there is a dire need for a massive number of GPUs. Indian universities barely have the necessary infrastructure for AI research. Meanwhile, the total amount of research funding that Indian universities receive, China spends on just two universities.  The government’s hesitation to invest more in research is due to the low base of research spending, coupled with bureaucratic hurdles in spending allocated funds. This vicious circle hampers innovation and research in India, but unfortunately, it’s a topic that receives little attention. Ease of doing research, is something that needs to be carefully evaluated for these funding schemes to be effective, he added. He said that investing so much in a country where the infrastructure is not up to the global standards is a challenge for big companies.

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🎉😀🎉 We are delighted to share that our recent article "Intrinsic spin Hall and Rashba effects in metal nitride bromide monolayer for spin-orbitronics" is now published in the Journal of Applied Physics. Investigating the interplay between charge and spin conversion in two-dimensional (2D) materials holds significant promise for futuristic electronic applications. Through density functional theory, our study delves into the charge-spin conversion and spin density dynamics in the non-magnetic SnNBr monolayer under time-reversal invariance. The breaking of out-of-plane mirror symmetry and inversion symmetry, along with the presence of spin–orbit coupling (SOC) lead to a notable momentum-dependent spin band splitting or Rashba effect induced by the inherent out-of-plane electric field. Theoretical calculations reveal not only the presence of profound Rashba spin splitting but also the coexistence of intrinsic spin Hall effects in the SnNBr monolayer. Analysis of k-resolved spin Berry curvature sheds light on the origin of the substantial intrinsic spin Hall conductivity. Furthermore, our research highlights the modulation of charge-to-spin conversion and spin density accumulation through in-plane biaxial strains. Moreover, the variation in the Rashba parameter is correlated with the changes in the built-in out-of-plane electric field and microscopic atomic orbital contributions. These findings underscore the exceptional potential of the non-centrosymmetric SnNBr monolayer for advanced spintronics, spin-orbitronics, and piezo-spintronic applications, and serve as a catalyst for further experimental investigations. Reference: J. Appl. Phys. 135, 234302 (2024) DOI: https://lnkd.in/gmWEKS3g

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Application of #Siproin #SST-#MRAM in #SSD Card STT-MRAM is an ideal device for non-volatile cache and main memory. It has great advantages for high reliability applications , such as intelligent, non-volatile and fast read/ write capability which could be used in SSD. The application characteristics of STT-MRAM in SSD: 🏷️ STT-MRAM (Spin-Transfer Torque Magnetoresistive Random Access #Memory) enables the implementation of larger write buffers in Solid State Drives (SSDs). This feature not only reduces energy consumption but also enhances the reliability and manufacturability of SSDs. The large, low-latency write buffers implemented in STT-MRAM can effectively mitigate write amplification and improve the endurance of flash memory arrays. 🏷️ STT-MRAM provides a hierarchical Flash Translation Layer (FTL) non-volatile storage solution, which simplifies the design of controllers and shortens the recovery time after power failures. 🏷️ The utilization of STT-MRAM offers persistent storage for local, low-latency Consistency Memory Barriers (CMBs), simplifying the task of integrating this extensive capability into SSD drives. 🏷️ STT-MRAM allows SSD designers to optimize packaging, performance, endurance, and reliability, while reducing complexity and enabling advanced features. It presents a superior alternative to DRAM-based SSD controller architectures for next-generation enterprise SSDs. The main programs in SSD : 💡 Option 1: 📌 Adding small-capacity MRAM 📌 Added between the bus of the controller and DRAM 📌 64Mb and above MRAM 📌 Increased available space improves overall performance/reliability 💡 Option 2: 📌 Large-capacity MRAM replaces DRAM 📌 1/1000 of the capacity of flash memory 📌 Increased usable space 📌 Improved overall performance/reliability 📌 Completely eliminates energy storage devices such as capacitors 📌 Reduced boot recovery time More datails could be able to visit our webiste: https://lnkd.in/gpxeywp7 or get in touch with us to learn more. 🤩

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How VLSI is Shaping the Future of Everyday Devices You might not realize it, but VLSI technology is what’s behind almost all modern gadgets—phones, tablets, cars, and even medical devices. Here’s why it’s crucial: 1. Power Efficiency: Less energy usage means longer battery life for devices. 2. Miniaturization: VLSI allows for smaller gadgets without compromising performance. 3. Faster Processing: Devices powered by VLSI can handle complex tasks much quicker. In short, VLSI is about making the tech in your life smarter, more powerful, and more affordable. The devices we use every day wouldn’t be as advanced without it.

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✅ CMOS, FinFET, GAAFET, and Emerging Transistor Technologies ✅ Most recommended for Undergraduates and VLSI Aspirants, do follow for daily updates Outline • What is Moore’s Law • Nano-Meter Technology • CMOS Technology • FinFET Technology • GAAFET Technology 👉 👉 Please do follow & do share 👉 👉 For more information do follow ProV Logic or Prasanthi Chanda

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