Deepthy Sivan

Common Resource Block (CRB) in 5G-NR 1. CRBs are set of RBs which occupy channel bandwidth and they are defined for each subcarrier spacing. 2. CRBs provide the RB numbering throughout the carrier bandwidth while PRBs provide RB numbering within each BWP. 3. They are numbered from 0 in upward direction where CRB 0 is located at lower side of Channel Bandwidth. 4. The CRBs associated with each and every SCS are aligned at Point A  i.e., the center of subcarrier 0 of CRB 0 for each subcarrier spacing coincides with Point A. 5. From figure, the CRB edges for different SCS are not aligned. The CRB edge with SCS = 2∆f is shifted by ∆f kHz as compared to CRB edge with SCS= ∆f. For example, the CRB edge with SCS= 30kHz is shifted by 7.5kHz as compared to CRB edge with SCS= 15kHz. 6. UE determines the position of 'Point A' using ARFCN provided by SIB1 or dedicated signalling from gNB. SIB1 provides the FrequencyInfoDL-SIB parameter including IE "offset to carrier value" specifying the number of RBs between 'Point A' and subcarrier 0 and also IE 'carrierBandwidth' that specifics the number of RBs which are available.  #5g #5gnetwork #5gnr #communication #5gtechnology

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Top 100 HiL hardware in loop Interview Questions With Answers For Engineers Question 01: What is Hardware-in-the-Loop (HiL) Testing? Answer: HiL testing is a technique used in the development and validation of embedded systems where real hardware components (such as controllers, sensors, or actuators) are connected to a simulation environment. This allows for testing and validating the interaction of hardware with simulated components under controlled conditions. Question 02: What are the Advantages of HiL Testing? Answer: The advantages of HiL testing include: Early detection of issues in the development cycle. Cost-effective validation of complex systems. Ability to simulate a wide range of scenarios without physical prototypes. Safer testing environment for critical systems. Question 03: Can you describe the typical components of a HiL test setup? Answer: A HiL test setup typically includes: Real hardware components (controllers, ECUs, sensors, actuators). Simulation models representing the environment or systems. Real-time computing platform for executing simulation models. I/O interfaces to connect hardware with simulation. Test automation software and monitoring tools. Question 04: How does HiL testing differ from other testing methodologies like SiL (Software-in-the-Loop) or MiL (Model-in-the-Loop)? Answer: HiL testing involves testing real hardware components in simulated environments, while SiL focuses on testing software components in a simulated environment without real hardware. MiL testing primarily uses simulation models to test system behavior. Question 05: What factors are important when selecting simulation models for HiL testing? Answer: When selecting simulation models for HiL testing, consider: Accuracy and fidelity of the models. Compatibility with the real-time execution platform. Ability to simulate complex behaviors and interactions. Efficiency to meet real-time constraints. Question 06: How do you ensure real-time performance in a HiL test setup? Answer: Real-time performance in HiL testing is ensured by: Optimizing simulation models for efficiency. Using high-performance real-time computing hardware. Implementing deterministic scheduling and data exchange mechanisms. Minimizing latency in I/O interfaces. Question 07: What challenges have you encountered in HiL testing, and how did you overcome them? Answer: Common challenges in HiL testing include synchronization issues, model fidelity, and hardware-software integration problems. Overcoming these challenges often involves iterative testing, model refinement, and close collaboration between hardware and software teams. . . . #HiL #Hardwareinloop #Electronics #MiL #SiL #MATLAB #Automotive #Engineers #Software #Coder #Interviewquestions

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🔌 Understanding Bridge Rectifiers in Embedded Systems 🔌 In the world of embedded systems, efficient power conversion is critical for reliable operation. One key component that plays a pivotal role in converting AC to DC is the Bridge Rectifier. But what exactly is it, and why is it so important? 🤔 📚 What is a Bridge Rectifier? A bridge rectifier is an arrangement of four diodes in a bridge configuration that converts alternating current (AC) to direct current (DC). Unlike half-wave or full-wave rectifiers, which use fewer diodes, the bridge rectifier offers a full-wave rectification without requiring a center-tapped transformer. This makes it a more efficient and space-saving solution. ⚙️ How Does It Work? The bridge rectifier works by directing the current through four diodes in such a way that the output is always of the same polarity, regardless of the input AC phase. During the positive half-cycle of the AC input, two diodes conduct and direct the current through the load in one direction. During the negative half-cycle, the other two diodes conduct, maintaining the same direction of current flow through the load. 💡 Key Benefits in Embedded Systems: 1. Full-Wave Rectification: Utilizes both halves of the AC waveform, resulting in higher efficiency and reduced ripple. 2. No Need for a Center-Tapped Transformer: Simplifies design and reduces cost and space. 3. High Reliability: Bridge rectifiers are robust, ensuring consistent performance in various applications. 🛠 Applications: Power Supply Units: Converts AC mains to the DC voltage required by embedded circuits. Motor Controllers: Ensures smooth and efficient operation of DC motors. Battery Chargers: Provides the necessary DC voltage to charge batteries from an AC source. In essence, bridge rectifiers are fundamental in ensuring that embedded systems receive a steady and reliable DC power supply, contributing to the overall stability and efficiency of electronic devices. Whether you’re designing a simple microcontroller circuit or a complex IoT device, understanding the role of bridge rectifiers can help you create more robust and reliable systems. 🌐💪 #EmbeddedSystems #PowerElectronics #BridgeRectifier #ElectricalEngineering #IoT #CircuitDesign

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𝐔̲𝐧̲𝐝̲𝐞̲𝐫̲𝐬̲𝐭̲𝐚̲𝐧̲𝐝̲𝐢̲𝐧̲𝐠̲ ̲𝐭̲𝐡̲𝐞̲ ̲𝐒̲𝐞̲𝐜̲𝐮̲𝐫̲𝐢̲𝐭̲𝐲̲ ̲𝐑̲𝐢̲𝐬̲𝐤̲𝐬̲ ̲𝐢̲𝐧̲ ̲𝐔̲𝐧̲𝐢̲𝐟̲𝐢̲𝐞̲𝐝̲ ̲𝐃̲𝐢̲𝐚̲𝐠̲𝐧̲𝐨̲𝐬̲𝐭̲𝐢̲𝐜̲ ̲𝐒̲𝐞̲𝐫̲𝐯̲𝐢̲𝐜̲𝐞̲𝐬̲ ̲(̲𝐔̲𝐃̲𝐒̲)̲ ̲𝐏̲𝐫̲𝐨̲𝐭̲𝐨̲𝐜̲𝐨̲𝐥̲ ̲🚗 The Unified Diagnostic Services (UDS) protocol is a powerful tool in automotive diagnostics, enabling a diagnostic client—whether an external service tool or an internal ECU—to access crucial vehicle services. From aggregating fault data to initiating programming sessions, UDS plays a central role in modern vehicle operation. It relies on transport protocols like CAN, enabling segmented message transmission. While UDS is essential for vehicle maintenance and service, it can also open doors to potential cyberattacks. Let's explore some critical attack vectors associated with the UDS protocol: 🔒 𝐌𝐚𝐧𝐢𝐩𝐮𝐥𝐚𝐭𝐢𝐨𝐧 𝐨𝐟 𝐕𝐞𝐡𝐢𝐜𝐥𝐞 𝐂𝐨𝐝𝐞 & 𝐃𝐚𝐭𝐚: By exploiting services like requestDownload and TransferData, an attacker can initiate flash programming, while RoutineControl allows memory erasure. 🔒 𝐕𝐞𝐡𝐢𝐜𝐥𝐞 𝐂𝐨𝐝𝐞 & 𝐃𝐚𝐭𝐚 𝐄𝐱𝐭𝐫𝐚𝐜𝐭𝐢𝐨𝐧: The requestUpload service, designed to read out code or firmware, can be abused to extract sensitive vehicle information. 🔒 𝐕𝐞𝐡𝐢𝐜𝐥𝐞 𝐌𝐨𝐝𝐞 𝐌𝐚𝐧𝐢𝐩𝐮𝐥𝐚𝐭𝐢𝐨𝐧: A malicious actor could trigger a soft or hard reset via the resetECU request—this could have dire consequences if initiated while the vehicle is in motion. 🔒 𝐕𝐞𝐡𝐢𝐜𝐥𝐞 𝐏𝐚𝐫𝐚𝐦𝐞𝐭𝐞𝐫 𝐓𝐚𝐦𝐩𝐞𝐫𝐢𝐧𝐠: The WriteDataByIdentifier service allows parameter manipulation, such as changing odometer values, leading to financial or legal risks. 🔒 𝐕𝐞𝐡𝐢𝐜𝐥𝐞 𝐎𝐩𝐞𝐫𝐚𝐭𝐢𝐨𝐧 𝐓𝐚𝐦𝐩𝐞𝐫𝐢𝐧𝐠: Misusing diagnostic routines for actuation—meant for troubleshooting—during vehicle operation could compromise vehicle safety. 🔒 𝐕𝐞𝐡𝐢𝐜𝐥𝐞 𝐂𝐨𝐧𝐟𝐢𝐠𝐮𝐫𝐚𝐭𝐢𝐨𝐧 𝐓𝐚𝐦𝐩𝐞𝐫𝐢𝐧𝐠:  During vehicle assembly or service, diagnostic routines are used to configure settings or provision cryptographic secrets. If abused, these routines can result in unsafe or insecure configurations. In addition to these service-specific risks, it's important to consider the underlying transport protocol. Carefully crafted malicious messages can violate protocol requirements, leading to connection terminations and other vulnerabilities. By understanding the services UDS provides and the potential threats they introduce, we can better safeguard vehicles from exploitation. I encourage everyone in the automotive cybersecurity field to dive deeper into the transport protocols and explore ways to mitigate these risks. #AutomotiveCybersecurity #UDS #VehicleDiagnostics #CyberThreats #CANProtocol #TransportProtocol

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Capabilities for Designing Feedback Control Systems Explore what is possible with MATLAB and Simulink Free Courses : https://lnkd.in/dnBskgY2

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This paper explores the #direction-#of-#arrival (#DOA) estimation problem and examines the inherent signal structures. Subsequently, two DOA estimation algorithms based on a dynamic-dictionary sparse representation are developed, namely the #Jointly-#Selected #Orthogonal #Matching #Pursuit (#JSOMP) algorithm and the #Auxiliary #Variable #Joint #Alternating #Optimization (#AVJAO) algorithm. ----@Liang Liu, @Zhouchen Li, Jiancheng An, @Lu Gan, @Hongbin Li https://lnkd.in/gFMeEciK

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RNTI in 5G-NR Based on different stage/requirements gNB give these RNTI to UE and they are used to de-scramble the CRC bits attached to DCI which let UE decode the messages. Also, all RNTI have a length of 16 bits. Different RNTIs are as follow: 1. C-RNTI : After successful Random Access contention resolution, it is given to UE. The C-RNTI is reconfigured whenever a UE completes a handover towards a new cell. 2. P-RNTI : Is used to scramble the CRC bits belonging to DCI Format 1_0 when allocating PDSCH resources for the transmission of Paging messages. It can also be used to indicate an Earthquake and Tsunami Warning. 3. SI-RNTI : It is used to scramble the CRC bits belonging to DCI Format 1_0 when allocating PDSCH resources for the transmission of System Information. 4. RA-RNTI : Used when allocating PDSCH resources for the transmission of RAR (MSG2), DCI Format 1_0. 5. I-RNTI : It is not used to scramble the CRC bits belonging to the PDCCH payload. lnstead, the I-RNTI is used to address the UE within RRC signalling messages. It can be allocated to a UE within an RRCRelease message when moving the UE from RRC Connected to RRC Inactive state. 6. TPC-PUSCH-RNTI, TPC-PUCCl-I-RNTI and TPC-SRS-RNTI : They are used to provide Transmit Power Control (TPC) commands for the PUSCH, PUCCH and SRS respectively. DCI Formats 2_2 and 2_3 arc able to provide TPC commands for a group of UE rather than only a single UE. #5g #5gnr #network #communication #technology

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Are you curious about the difference between GCC and Clang compilers? Check out this informative video made by me! Many companies use one or the other, but not everyone knows the differences because people will be more focused on application development over compiler itself. With curiosity comes the continuous learning and this leads to knowledge expansion😉. Happy leaning... https://lnkd.in/g-_cEud7

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Hi folks, for decades, C and C++ have reigned supreme in embedded systems. But with Python's rise, a new challenger has emerged. Let's dissect their strengths and considerations for a nuanced view. 𝗖/𝗖++ 𝗣𝗿𝗼𝘀: Performance: Unmatched speed and fine-grained control over hardware resources. Ideal for real-time, low-latency applications. Memory Management: Direct memory access allows for extreme optimization, crucial for resource-constrained devices. Legacy Codebase: Enormous existing codebase in C/C++, facilitating maintenance and integration. 𝗖𝗼𝗻𝘀: Development Time: Complex syntax and manual memory management increase development effort. Portability: Requires careful platform-specific coding, hindering code reuse across diverse embedded systems. Debugging: Memory errors can be challenging to pinpoint due to manual management. 𝗣𝘆𝘁𝗵𝗼𝗻 𝗣𝗿𝗼𝘀: ● Readability & Maintainability: Concise syntax promotes clear code, reducing long-term maintenance costs. ● Development Speed: Rapid prototyping and iteration cycles due to high-level abstractions. ● Portability: "Write once, run anywhere" philosophy simplifies code reuse across different embedded systems. 𝗖𝗼𝗻𝘀: ● Performance: Generally slower execution compared to C/C++. May not be suitable for highly performance-critical tasks. ● Resource Usage: Larger memory footprint can be an issue for very limited embedded devices. ● Limited Hardware Control: Python's abstraction layer can restrict direct hardware access, crucial for some low-level operations. 𝗧𝗵𝗲 𝗩𝗲𝗿𝗱𝗶𝗰𝘁: 𝗔 𝗦𝗽𝗲𝗰𝘁𝗿𝘂𝗺, 𝗡𝗼𝘁 𝗮 𝗗𝗶𝗰𝗵𝗼𝘁𝗼𝗺𝘆 The choice between Python and C/C++ hinges on project requirements. Here's a breakdown: ● C/C++ remains king for: Real-time systems, performance-critical applications, and highly resource-constrained devices. ● Python shines in: Rapid prototyping, user-facing interfaces on embedded systems, and projects prioritizing readability and maintainability. 𝗜𝗻𝗻𝗼𝘃𝗮𝘁𝗶𝗼𝗻 𝗮𝗻𝗱 𝘁𝗵𝗲 𝗙𝘂𝘁𝘂𝗿𝗲 MicroPython and CircuitPython aim to bridge the gap. These optimized Python variants target microcontrollers, offering a balance between Python's ease of use and some hardware access. The future may see these lightweight implementations expand Python's reach in embedded systems. Ultimately, the best choice depends on a thorough analysis of your specific project needs. Both languages offer valuable tools, and a measured approach can lead to efficient and innovative embedded system development. What are your thoughts on Python's growing role in embedded systems? Have you used MicroPython or CircuitPython in your projects? For C/C++ developers, are there scenarios where you see Python as a complementary tool? Share your experiences in the comments below! #Python #C #C++ #EmbeddedSystems #Programming #EmbeddedSystems #EngineeringRecruitment #EmbeddedRecruiter #RunTimeRecruitment

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🚀 Excited to share an insightful paper by Nidhi Singh! The paper introduces the Transformer model, which relies entirely on a mechanism called "self-attention" to draw global dependencies between input and output. This approach eliminates the need for recurrent and convolutional networks, which were commonly used in sequence modeling tasks. Read more here: Embeddings in Transformer Architecture https://lnkd.in/giVTAK4b #AI #Transformers #MachineLearning #ProCodebase #SelfAttention #DeepLearning #NLP

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👉 Training: Generating HDL Code from Simulink Learn how to create Simulink models for HDL code generation, generate HDL code, and optimize Simulink models. https://spr.ly/6045tVKDB

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🚀 dSPACE Hardware-in-the-Loop (HiL) Testing Simplified 🌟 HiL testing is a game-changer for validating and verifying embedded systems. With dSPACE, you can simulate real-world scenarios and test control systems without the risk of damaging actual hardware. 💡 From creating plant models in MATLAB Simulink to real-time execution on dSPACE hardware, the process ensures accuracy and efficiency. ControlDesk becomes your ultimate companion for real-time monitoring, parameter tuning, and fault injection. 🔧 Whether you're testing powertrains, ADAS systems, or battery management, dSPACE provides unmatched precision and scalability. Plus, automation tools like AutomationDesk streamline complex test cases for faster results. 🚘 Say goodbye to late-stage bugs and hello to early detection, cost savings, and reliable systems! 🖥️✨ #HiLTesting #dSPACE #AutomotiveEngineering #MATLAB #EmbeddedSystems #RealTimeSimulation #Innovation #TechPost #Electronics #EEE #Electrical #Engineers #ChetanShidling #CSElectricalAndElectronics #Coding

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As we are on verge of completion of our First Autosar MCAL Layer Course: AutoCalV1(https://lnkd.in/gZMnypZK), we will be starting with new series on Different Sensor/Module interfacing using Autosar MCAL Driver Layer via Gettobyte Technologies Pvt. Ltd. #ElecronicsV3 and #AutoboardV1 boards. Objective of this series is going 𝐭𝐨 𝐛𝐞 𝐜𝐫𝐞𝐚𝐭𝐢𝐨𝐧 𝐨𝐟 𝐝𝐫𝐢𝐯𝐞𝐫𝐬 𝐨𝐟 𝐰𝐢𝐝𝐞 𝐫𝐚𝐧𝐠𝐞 𝐨𝐟 𝐚𝐮𝐭𝐨𝐦𝐨𝐭𝐢𝐯𝐞 𝐬𝐞𝐧𝐬𝐨𝐫𝐬 𝐚𝐧𝐝 𝐦𝐨𝐝𝐮𝐥𝐞𝐬 𝐟𝐫𝐨𝐦 𝐬𝐜𝐫𝐚𝐭𝐜𝐡 𝐮𝐬𝐢𝐧𝐠 𝐀𝐮𝐭𝐨𝐬𝐚𝐫 𝐌𝐂𝐀𝐋 𝐃𝐫𝐢𝐯𝐞𝐫𝐬 𝐰𝐢𝐭𝐡 𝐚𝐧 𝐚𝐮𝐭𝐨𝐦𝐨𝐭𝐢𝐯𝐞 𝐌𝐂𝐔 and learning how those sensor/module work via Handson DIY way Through our Hardware Kits and Boards. 𝐔𝐥𝐭𝐢𝐦𝐚𝐭𝐞 𝐦𝐨𝐭𝐨 𝐢𝐬 𝐭𝐨 𝐜𝐫𝐞𝐚𝐭𝐞 𝐚 𝐜𝐨𝐦𝐩𝐥𝐞𝐭𝐞 𝐞𝐜𝐨𝐬𝐲𝐬𝐭𝐞𝐦/𝐟𝐫𝐚𝐦𝐞𝐰𝐨𝐫𝐤 𝐚𝐫𝐨𝐮𝐧𝐝 𝐝𝐢𝐟𝐟𝐞𝐫𝐞𝐧𝐭 𝐚𝐮𝐭𝐨𝐦𝐨𝐭𝐢𝐯𝐞 𝐭𝐞𝐜𝐡𝐧𝐨𝐥𝐨𝐠𝐢𝐞𝐬 𝐭𝐨 𝐥𝐞𝐚𝐫𝐧 𝐭𝐡𝐞𝐦 𝐢𝐧 𝐃𝐈𝐘 𝐇𝐚𝐧𝐝𝐬𝐨𝐧 𝐰𝐚𝐲, 𝐚𝐧𝐝 𝐧𝐨𝐭 𝐣𝐮𝐬𝐭 𝐭𝐡𝐞𝐨𝐫𝐞𝐭𝐢𝐜𝐚𝐥 𝐚𝐧𝐝 𝐏𝐏𝐓 𝐛𝐚𝐬𝐞𝐝. Explore the course landing and subscribe to it for free, to get its latest and all upcoming updates!!! https://lnkd.in/gM6DvmhH #automotive #semiconductor #embedded #learn #skill #college #nxp #s32k144 #s32k344

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Commonly used Temporal System Functions in SystemVerilog Assertions $rose, $fell, $past, $stable, $changed Temporal system functions in SystemVerilog are special built-in functions used in assertions to check and track signal behavior over time. This function allows user to check behavior of system over multiple clock cycles. In hardware verification, you often need to check whether a signal behaves as expected not just in a single clock cycle but across multiple cycles. Temporal system functions simplify this by allowing assertions to track signals over time. Typical used cases for temporal function include: 1) Detect changes in signals across clock cycles. 2) Monitor signal stability over a period. 3) Check for signal transitions, such as rising or falling edges. 4) Capture past values of signals. Commonly use system functions include: 1) $past(expression/signal, n): returns the value of a signal from n clock cycles ago. 2) $stable(expression/signal): Checks if the value of a signal has stayed the same for a specified number of clock cycles. 3) $rose(expression): Detects if a signal has a rising edge (transition from 0 to 1). 4) $fell(expression): Detects if a signal has a falling edge (transition from 1 to 0). 5) $changed(expression): Detects if the signal value changed in the current clock cycle. Learn everything about SV assertions and Coverage here : https://lnkd.in/g7ADW7HV

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🚀 Engineers: Join our upcoming webinar, "Innovative GSPS Signal Processing with MATLAB & Simulink for FPGA & SoC"! Dive deep into cutting-edge solutions and enhance your skills. 🛠️ 📅 Mark your calendars: May 8th 🔗 Register now! #Engineering #MATLAB #SignalProcessing

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How to use fcn block in simulink fcn The "Fcn" block in Simulink implements custom mathematical functions or expressions, enhancing modeling flexibility. https://lnkd.in/gfF96Yea https://lnkd.in/gf7mDhjs #Simulink #FcnBlock #CustomFunction #MathematicalModeling #Simulation #ControlSystems #SignalProcessing #Engineering #Modeling #ElectricalEngineering #Mathematics #SimulinkLibrary #ModelingFlexibility #SimulationModel #ExpressionBlock

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