[spi_device] TPM interrupt for Write FIFO

[eunchan]

Related Issue: #15773

Current TPM IP does not provide an interrupt about the write transaction completion. Absent of the interrupt results the SW to wait until the transaction completed by reading the WrFIFO depth or polling the TPM CS# de-assertion.

A TPM transaction may took up to 55 us (64B + 1 Wait + address + cmd @ 10MHz). By introducing the completion interrupt for the Write FIFO, SW can switch the context.

Idea suggested by @tjaychen

CC: @weicaiyang @tjaychen @a-will

estimate 16
remaining 2023-03-21 16

[andreaskurth]

Triaged for spi_device. Assigning to M2.5 with Priority:P2 Priority: medium , though I'm not sure (1) whether this would free clock cycles on Ibex or on the TPM and (2) how this relates to requirements and capabilities of the product. Maybe @a-will knows? If not, I'll bring this up for discussion with the product team.

[a-will]

Triaged for spi_device. Assigning to M2.5 with Priority:P2 Priority: medium , though I'm not sure (1) whether this would free clock cycles on Ibex or on the TPM and (2) how this relates to requirements and capabilities of the product. Maybe @a-will knows? If not, I'll bring this up for discussion with the product team.

1. This frees up cycles on Ibex. The current design only has an interrupt to inform software when the command and address phase completes (the "header"), but the transaction continues afterwards, potentially for a substantial amount of time (for the 64-byte payload case, especially).

2. For a SPI TPM that only does 4-byte payloads, the thinking (in the IP doc) was that the transmission time is too short for an interrupt to be useful. However, as payloads grow larger, the time duration grows larger, potentially making busy-waiting expensive. For the sake of prioritization, the product team may be helpful for determining which payload sizes are important.

[hcallahan-lowrisc]

Conclusion from product team feedback:

• add interrupt on CSb deassertion after write command (write completion)
• add interrupt after read command + header (read completion)

Estimate to cover RTL changes + DV

estimate 16
remaining 2023-03-21 16

[jesultra]

As far as I know the only TPM register which is wider than 4 bytes is the FIFO register. That is used all the time, though. If we do not get interrupt at the end of a transaction involving the GSC receiving data through the FIFO register, that would be a problem.
We could busy-wait, but doing so would adversely affect our ability to verify performance of other aspects of our code, such as whether forwarding of characters from UART to USB encounters data loss during other system activity

[johngt]

Based on prioritisation discussion - this RTL change will likely need to go into the next cycle and use the SW workaround.
De-prioritising accordingly. If this does need to go in then it should be re-raised as a P0 @jesultra / @moidx / @msfschaffner / @GregAC

[moidx]

We missed the window for RTL changes, we'll move this to the backlog so that it can be considered for the next RTL freeze.