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1. caravel_user_project caravel_user_project Public template

   https://caravel-user-project.readthedocs.io

   Verilog 183 329

2. caravel_user_project_analog caravel_user_project_analog Public template

   Verilog 45 90

3. mpw_precheck mpw_precheck Public

   Python 37 24

4. caravel caravel Public

   Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

   Verilog 295 69

5. caravel_board caravel_board Public

   C 32 41

6. openframe_timer_example openframe_timer_example Public

   Forked from efabless/caravel_openframe_project

   Example digital project for the Efabless Caravel "openframe" harness

   Verilog 5 4