An update on Keccak performance on ARMv7-M

Alexandre Adomnicai

Paper 2023/773

An update on Keccak performance on ARMv7-M

Alexandre Adomnicai

Abstract

This note provides an update on Keccak performance on the ARMv7-M processors. Starting from the XKCP implementation, we have applied architecture-specific optimizations that have yielded a performance gain of up to 21% for the largest permutation instance.

Note: Fix inconsistency in benchmark settings: STM32F746NG was clocked at 24MHz (not 30MHz).

Metadata

Available format(s): PDF
Category: Implementation
Publication info: A major revision of an IACR publication in TCHES 2024
DOI: 10.46586/tches.v2024.i2.1-24
Keywords: Keccak SHA-3 SHAKE ARMv7-M
Contact author(s): alexandre @ adomnicai me
History: 2024-05-15: revised; 2023-05-27: received; See all versions
Short URL: https://ia.cr/2023/773
License: CC0

BibTeX

@misc{cryptoeprint:2023/773,
      author = {Alexandre Adomnicai},
      title = {An update on Keccak performance on {ARMv7}-M},
      howpublished = {Cryptology {ePrint} Archive, Paper 2023/773},
      year = {2023},
      doi = {10.46586/tches.v2024.i2.1-24},
      url = {https://eprint.iacr.org/2023/773}
}