Skip to main content
Log in

Design and Results of the First Satisfiability Modulo Theories Competition (SMT-COMP 2005)

  • Published:
Journal of Automated Reasoning Aims and scope Submit manuscript

Abstract

The Satisfiability Modulo Theories Competition (SMT-COMP) is intended to spark further advances in the decision procedures field, especially for applications in hardware and software verification. Public competitions are a well-known means of stimulating advancement in automated reasoning. Evaluation of SMT solvers entered in SMT-COMP took place while CAV 2005 was meeting. Twelve solvers were entered; 1,352 benchmarks were collected in seven different divisions.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

Explore related subjects

Discover the latest articles, news and stories from top researchers in related subjects.

References

  1. Ackermann, W.: Solvable cases of the decision problem. Studies in Logic and the Foundation of Mathematics, pp. 102–103. North-Holland, Amsterdam (1954)

  2. Armando, A., Castellini, C., Giunchiglia, E., Maratea, M.: A SAT-based decision procedure for the boolean combination of difference constraints. In: The 7th International Conference on Theory and Applications of Satisfiability Testing (2004)

  3. Armando, A., Ranise, S., Rusinowitch, M.: A rewriting approach to satisfiability procedures. Inf. Comput. 183(2), 140–164 (June 2003). Special Issue on the 12th International Conference on Rewriting Techniques and Applications (RTA 2001)

    Article  MATH  MathSciNet  Google Scholar 

  4. Barrett, C., Dill, D., Stump, A.: A framework for cooperating decision procedures. In: McAllester, D. (ed.) 17th International Conference on Automated Deduction, pp. 79–97. Springer, Berlin Heidelberg New York (2000)

  5. Barrett, C., Dill, D., Stump, A.: Checking satisfiability of first-order formulas by incremental translation to SAT. In: 14th International Conference on Computer-Aided Verification (2002)

  6. Barrett, C.: Checking validity of quantifier-free formulas in combinations of first-order theories. Ph.D. thesis, Stanford University (2003)

  7. Barrett, C., Berezin, S.: CVC Lite: A new implementation of the cooperating validity checker. In: Alur, R., Peled, D.A. (eds.) Proceedings of the 16th International Conference on Computer Aided Verification (CAV '04), vol. 3114 of Lecture Notes in Computer Science, pp. 515–518. Springer, Berlin Heidelberg New York (July 2004)

    Google Scholar 

  8. Barrett, C.W., Dill, D.L., Levitt, J.R.: Validity checking for combinations of theories with equality. In: Srivas, M., Camilleri, A. (eds.) Proceedings of the 1st International Conference on Formal Methods In Computer-Aided Design (FMCAD '96), vol. 1166 of Lecture Notes in Computer Science, pp. 187–201. Springer, Berlin Heidelberg New York (November 1996)

    Chapter  Google Scholar 

  9. CVC Lite website. http://verify.stanford.edu/CVCL

  10. Le Berre, D., Simon, L.: The essentials of the SAT 2003 Competition. In: Sixth International Conference on Theory and Applications of Satisfiability Testing, vol. 2919 of LNCS, pp. 452–467. Springer, Berlin Heidelberg New York (2003)

  11. Bjesse, P., Leonard, T., Mokkedem, A.: Finding bugs in an alpha microprocessor using satisfiability solvers. In: Berry, G., Comon, H., Finkel, A. (eds.) 13th Conference on Computer-Aided Verification. Springer, Berlin Heidelberg New York (2001)

  12. Clarke, E., Biere, A., Raimi, R., Zhu, Y.: Bounded model checking using satisfiability solving. Form. Methods Syst. Des. 19(1), 7–34 (2001)

    Article  MATH  Google Scholar 

  13. Das, S., Dill, D.L.: Counter-example based predicate discovery in predicate abstraction. In: Formal Methods in Computer-Aided Design. Springer, Berlin Heidelberg New York (November 2002)

  14. Eén, N., Sörensson, N.: An extensible SAT-solver. In: Proceedings of the Sixth International Conference on Theory and Applications of Satisfiability Testing (SAT 2003), vol. 2919 of Lecture Notes in Computer Science, pp. 502–518. Springer, Berlin Heidelberg New York (May 2003)

  15. Filliâtre, J., Owre, S., Rueß, H., Shankar, N.: ICS: Integrated canonizer and solver. In: Berry, G., Comon, H., Finkel, A. (eds.) 13th International Conference on Computer-Aided Verification, vol. 2102 of Lecture Notes in Computer Science, pp. 246–249. Springer, Berlin Heidelberg New York (2001)

  16. Flanagan, C., Leino, K., Lillibridge, M., Nelson, G., Saxe, J., Stata, R.: Extended static checking for Java. SIGPLAN Not. 37, 234–245 (2002)

    Article  Google Scholar 

  17. Ganzinger, H., Hagen, G., Nieuwenhuis, R., Oliveras, A., Tinelli, C.: DPLL(T): Fast decision procedures. In: Proceedings of the 16th International Conference on Computer Aided Verification (CAV'04), vol. 3114 of Lecture Notes in Computer Science, pp. 175–188. Springer, Berlin Heidelberg New York (2004)

  18. Lahiri, S., Bryant, R., Goel, A., Talupur, M.: Revisiting positive equality. In: Tools and Algorithms for the Construction and Analysis of Systems, volume 2988 of Lecture Notes in Computer Science, pp. 1–15. Springer, Berlin Heidelberg New York (2004)

  19. Lerner, S., Millstein, T., Chambers, C.: Automatically proving the correctness of compiler optimizations. In: Gupta, R. (ed.) ACM SIGPLAN Conference on Programming Language Design and Implementation (2003). Received best paper award.

  20. Levitt, J.: Formal verification techniques for digital systems. Ph.D. thesis, Stanford University (1999)

  21. Bozzano, M., Bruttomesso, R., Cimatti, A., Junttila, T., Rossum, P.v., Schulz, S., Sebastiani, R., The MathSAT 3 System. In: Proceedings of the 20th International Conference on Automated Deduction (July 2005)

  22. Möller, M., Rueß. H.: Solving bit-vector equations. In: Formal Methods in Computer-Aided Design, pp. 36–48 (1998)

  23. Nieuwenhuis, R., Oliveras, A.: DPLL(T) with exhaustive theory propagation and its application to difference logic. In: Proceedings of the 17th International Conference on Computer Aided Verification (CAV'05), Lecture Notes in Computer Science. Springer, Berlin Heidelberg New York (2005)

  24. Pelletier, F.J., Sutcliffe, G., Suttner, C.B.: The development of CASC. AI Commun. 15(2–3), 79–90 (2002)

    MATH  Google Scholar 

  25. Pnueli, A., Rodeh, Y., Strichman, O.: Range allocation for equivalence logic. In: 21st Conference on Foundations of Software Technology and Theoretical Computer Science, vol. 2245 of Lecture Notes in Computer Science, pp. 317–333. Springer, Berlin Heidelberg New York (2001)

  26. Ranise, S., Tinellim, C.: The SMT-lib standard, version 1.1, 2005. Available from the “Documents” section of http://combination.cs.uiowa.edu/smtlib

  27. Rueß, H., Shankar, N.: Solving linear arithmetic constraints. Technical Report SRI-CSL-04-01, SRI International (2004)

  28. Seshia, S., Bryant, R.: Deciding quantifier-free presburger formulas using parameterized solution bounds. In: Logic in Computer Science. IEEE (2004)

  29. Shankar, N.: Little engines of proof. Invited paper at Formal Methods Europe (2002)

  30. Sheini, H.M., Sakallah, K.A.: A SAT-based decision procedure for mixed logical/integer linear problems. In: Barták, R., Milano, M. (eds.) CPAIOR, vol. 3524 of Lecture Notes in Computer Science, pp. 320–335. Springer, Berlin Heidelberg New York (2005)

  31. Sheini, H.M., Sakallah, K.A.: A scalable method for solving satisfiability of integer linear arithmetic logic. In: Bacchus, F., Walsh, T., (eds.) SAT, vol. 3569 of Lecture Notes in Computer Science, pp. 241–256. Springer, Berlin Heidelberg New York (2005)

  32. Shlyakhter, I., Seater, R., Jackson, D., Sridharan, M., Taghdiri, M.: Debugging overconstrained declarative models using unsatisfiable cores. In: 18th IEEE International Conference on Automated Software Engineering (2003). Received best paper award

  33. Stump, A., Barrett, C., Dill, D., Levitt, J.: A decision procedure for an extensional theory of arrays. In: 16th IEEE Symposium on Logic in Computer Science, pp. 29–37. IEEE Computer Society (2001)

  34. Stump, A., Barrett, C.W., Dill, D.L.: CVC: A cooperating validity checker. In: Brinksma, E., Larsen, K.G. (eds.) Proceedings of the 14th International Conference on Computer Aided Verification (CAV '02), vol. 2404 of Lecture Notes in Computer Science, pp. 500–504. Springer, Berlin Heidelberg New York (July 2002)

    Google Scholar 

  35. Velev, M., Bryant, R.: Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors. J. Symb. Comput. 35(2), 73–106 (February 2003)

    Article  MATH  MathSciNet  Google Scholar 

  36. Zhang, H.: SATO: An efficient propositional prover. In: McCune, W. (ed.) Proceedings of the 14th International Conference on Automated deduction, vol. 1249 of Lecture Notes in Artificial Intelligence, pp. 272–275. Springer, Berlin Heidelberg New York (July 1997)

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Aaron Stump.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Barrett, C., de Moura, L. & Stump, A. Design and Results of the First Satisfiability Modulo Theories Competition (SMT-COMP 2005). J Autom Reasoning 35, 373–390 (2005). https://doi.org/10.1007/s10817-006-9026-1

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10817-006-9026-1

Key words

Navigation