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FPGA EDA

Design Principles and Implementation

  • Book
  • © 2024

Overview

Authors:
  1. Kaihui Tu

    1. Beijing, China

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  2. Xifan Tang

    1. Los Gatos, USA

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  3. Cunxi Yu

    1. University of Utah, Salt Lake City, USA

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  4. Lana Josipović

    1. ETH Zurich, Zürich, Switzerland

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  5. Zhufei Chu

    1. Ningbo University, Ningbo, China

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  • Offers a comprehensive overview on designing and implementing FPGA EDA tools
  • Bridges the gap between industrial and academic world
  • Presents the idea of the game-changing unified open-sourced FPGA EDA framework

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About this book

This book focuses on FPGA EDA tools, the very foundation of FPGA technology. Instead of illustrating how to use them, this book dives into the tools themselves, revealing how these tools are being designed and how they may improve. Unlike other semiconductors, FPGA has a distinctive two-stage EDA system: chip design EDA and application design EDA.State-of-the-art algorithms, data models and design methodologies/standards are the main concerns of this book, and these will be very helpful for FPGA EDA engineers and researchers to obtain a bird’s eye view of this complicated knowledge system. In the chip design EDA part, full-custom and semicustom methodologies bring up ASIC-like EDA tools, and in the application design EDA side, typical topics including high-level synthesis, logic synthesis, physical implementation, bitstream configuration, etc., are well discussed.

Keywords

Table of contents (12 chapters)

  1. Front Matter

    Pages i-xiii
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  2. Introduction

    1. Front Matter

      Pages 1-1
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    2. Introduction

      • Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu
      Pages 3-22

  3. FPGA Data Modeling

    1. Front Matter

      Pages 23-23
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    2. Device (Chip Design) Modeling

      • Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu
      Pages 25-47

    3. Design (Application Design) Modeling

      • Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu
      Pages 49-61

  4. FPGA Metric Analysis

    1. Front Matter

      Pages 63-63
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    2. Power Analysis

      • Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu
      Pages 65-71

    3. Performance (Timing) Analysis

      • Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu
      Pages 73-78

    4. Area Analysis

      • Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu
      Pages 79-82

  5. FPGA Chip Design EDA

    1. Front Matter

      Pages 83-83
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    2. Semi-custom EDA

      • Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu
      Pages 85-109

  6. FPGA Application Design EDA

    1. Front Matter

      Pages 111-111
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    2. High-Level Synthesis

      • Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu
      Pages 113-134

    3. Logic Synthesis

      • Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu
      Pages 135-164

    4. Physical Implementation

      • Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu
      Pages 165-206

    5. Bitstream Configuration

      • Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu
      Pages 207-221

  7. Summary and Outlook

    1. Front Matter

      Pages 223-223
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    2. Summary and Outlook

      • Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipović, Zhufei Chu
      Pages 225-227
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Authors and Affiliations

  • Beijing, China

    Kaihui Tu

  • Los Gatos, USA

    Xifan Tang

  • University of Utah, Salt Lake City, USA

    Cunxi Yu

  • ETH Zurich, Zürich, Switzerland

    Lana Josipović

  • Ningbo University, Ningbo, China

    Zhufei Chu

About the authors

​Kaihui Tu, MSc in Communications, University of York, York, UK. PhD in Microelectronics and Solid State Electronics, University of Chinese Academy of Sciences, Beijing, China. Tu has participated in numbers of Chinese national research projects, including China’s first 10K logic cell FPGA project, first embedded FPGA IP project and first TSV-based 3D FPGA project. With over ten years’ working experience in Chinese Academy of Sciences, Tu was responsible for architecting the eFPGA IP EDA tools that had won the “Made in China research IP Prize” at IP SoC China 2019.

Xifan Tang, PhD in Computer Science, graduated from École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland. CTO and cofounder of Rapid-Flex. Tang is also the maintainer of OpenFPGA project. 



Cunxi Yu, PhD in Computer Engineering, graduated from University of Massachusetts Amherst, Massachusetts, USA. Currently works as Assistant Professor at University of Maryland, College Park. Dr. Yu was Assistant Professor at University of Utah, and held PostDoc positions at Cornell and EPFL. 

Yu’s major academic honor includes: ACM/IEEE Design Automation Conference (DAC 2023) Best Paper Award • American Physics Society LPR Poster Honorable Mention (2022) • NSF CAREER Award (2021) • 2017 ASP-DAC Best Paper Nomination • ACM Doctoral Dissertation Award Nomination (by UMass Amherst) • DAC 2017 Security Contest - 1st Place.



Lana Josipovic currently works as Assistant Professor at ETH Zurich. She got her PhD in Computer and Communication Sciences graduated in 2021 from École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland. Dr. Josipovic’s major academic honor includes Best Paper Award Nominee at the 30th Intl. Symposium on Field-Programmable Custom Computing Machines (2022), Fritz Kutter Award for best Swiss industry-related PhD thesis in Computer Science, awarded by ETH Zurich (2021) , and Best Paper Award at the 28th Intl. Symposium on Field Programmable Gate Array (2020).


Zhufei Chu currently works as Professor at Ningbo University, China, and held PostDoc position at École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland. He is also the maintainer of open source logic synthesis project ALSO.

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