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Tullio Vardanega

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affiliation: University of Padua, Italy
affiliation: European Space Research & Technology Centre, Noordwijk, Netherlands

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2020 – today

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2024
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Edoardo Tinto, Tullio Vardanega:
A runtime infrastructure for the Continuum of Computing. HPDC 2024: 401-404
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Gabriele Pozzan, Costanza Padova, Chiara Montuori, Barbara Arfé, Tullio Vardanega:
Experimental Analysis of First-Grade Students' Block-Based Programming Problem Solving Processes. ITiCSE (1) 2024
2023
[c101]
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Marco Aldinucci, Elena Maria Baralis, Valeria Cardellini, Iacopo Colonnelli, Marco Danelutto, Sergio Decherchi, Giuseppe Di Modica, Luca Ferrucci, Marco Gribaudo, Francesco Iannone, Marco Lapegna, Doriana Medic, Giuseppa Muscianisi, Francesca Righetti, Eva Sciacca, Nicola Tonellotto, Mauro Tortonesi, Paolo Trunfio, Tullio Vardanega:
A Systematic Mapping Study of Italian Research on Workflows. SC Workshops 2023: 2065-2076
[c100]
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Enrico Nardelli, Francesco Lacchia, Renzo Davoli, Michael Lodi, Marco Sbaraglia, Veronica Rossano, Enrichetta Gentile, Violetta Lonati, Mattia Monga, Anna Morpurgo, Luca Forlizzi, Giovanna Melideo, Sara Capecchi, Ilenia Fronza, Tullio Vardanega:
Learning Iteration for Grades 2-3: Puzzles vs. UMC in Code.org. SIGCSE (2) 2023: 1368
2022
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Alberto Gutierrez-Torre, Kiyana Bahadori, Shuja Ur Rehman Baig, Waheed Iqbal, Tullio Vardanega, Josep Lluís Berral, David Carrera:
Automatic Distributed Deep Learning Using Resource-Constrained Edge Devices. IEEE Internet Things J. 9(16): 15018-15029 (2022)
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Mattia Bottaro, Tullio Vardanega:
Evaluating a multicore Mixed-Criticality System implementation against a temporal isolation kernel. J. Syst. Archit. 130: 102688 (2022)
[j21]
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Gabriele Pozzan, Tullio Vardanega:
Rafting multiplayer video games. Softw. Pract. Exp. 52(4): 1065-1091 (2022)
2021
[j20]
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Dilan Perale, Tullio Vardanega:
Removing bias from the judgment day: A Ravenscar-based toolbox for quantitative comparison of EDF-to-RM uniprocessor scheduling. J. Syst. Archit. 119: 102236 (2021)
2020
[j19]
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Barbara Arfé, Tullio Vardanega, Lucia Ronconi:
The effects of coding on children's planning and inhibition skills. Comput. Educ. 148: 103807 (2020)
[j18]
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Tullio Vardanega:
A new start: Introducing the journal-track proceedings of the 24th Ada-Europe conference on reliable software technologies. J. Syst. Archit. 111: 101852 (2020)

2010 – 2019

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2019
[j17]
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Francisco J. Cazorla, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernández, Jaume Abella, Tullio Vardanega:
Probabilistic Worst-Case Timing Analysis: Taxonomy and Comprehensive Survey. ACM Comput. Surv. 52(1): 14:1-14:35 (2019)
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Tullio Vardanega:
A Little Look Outside of the Box. MDE4IoT/ModComp@MoDELS 2019: 55-56
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Mirko Bez, Giacomo Fornari, Tullio Vardanega:
The Scalability Challenge of Ethereum: An Initial Quantitative Analysis. SOSE 2019
2018
[j16]
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Francisco J. Cazorla, Jaume Abella, Enrico Mezzetti, Carles Hernández, Tullio Vardanega, Guillem Bernat:
Reconciling Time Predictability and Performance in Future Computing Systems. IEEE Des. Test 35(2): 48-56 (2018)
[j15]
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Irune Agirre, Francisco J. Cazorla, Jaume Abella, Carles Hernández, Enrico Mezzetti, Mikel Azkarate-askatsua, Tullio Vardanega:
Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262. IEEE Trans. Reliab. 67(3): 1314-1327 (2018)
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Tullio Vardanega, Alberto Simioni:
In Pursuit of Architectural Agility: Experimenting with Microservices. SCC 2018: 113-120
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Stefano Munari, Sebastiano Valle, Tullio Vardanega:
Microservice-Based Agile Architectures: An Opportunity for Specialized Niche Technologies. Ada-Europe 2018: 158-174
[c95]
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Kiyana Bahadori, Tullio Vardanega:
Designing and Implementing Elastically Scalable Services - A State-of-the-art Technology Review. CLOSER 2018: 557-564
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Tullio Vardanega, Monica Fedeli:
A two-staged capstone project to foster university-business dialogue. ITiCSE 2018: 272-277
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Kiyana Bahadori, Tullio Vardanega:
DevOps Meets Dynamic Orchestration. DEVOPS 2018: 142-154
2017
[j14]
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Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla:
Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration. IEEE Trans. Computers 66(4): 586-600 (2017)
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Paolo Carletto, Tullio Vardanega:
Ravenscar-EDF: Comparative Benchmarking of an EDF Variant of a Ravenscar Runtime. Ada-Europe 2017: 18-33
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Suzana Milutinovic, Jaume Abella, Irune Agirre, Mikel Azkarate-askasua, Enrico Mezzetti, Tullio Vardanega, Francisco J. Cazorla:
Software Time Reliability in the Presence of Cache Memories. Ada-Europe 2017: 233-249
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Enrico Mezzetti, Mikel Fernández, Alen Bardizbanyan, Irune Agirre, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla:
EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application. RTAS 2017: 163-174
[c89]
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Suzana Milutinovic, Enrico Mezzetti, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla:
On uses of extreme value theory fit for industrial-quality WCET analysis. SIES 2017: 1-6
2016
[j13]
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Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Carles Hernández, Andrea Gianarro, Ian Broster, Francisco J. Cazorla:
Fitting processor architectures for measurement-based probabilistic timing analysis. Microprocess. Microsystems 47: 287-302 (2016)
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Laura Baracchi, Silvia Mazzini, Stefano Puri, Tullio Vardanega:
Lessons Learned in a Journey Toward Correct-by-Construction Model-Based Development. Ada-Europe 2016: 113-128
[c87]
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Francisco J. Cazorla, Jaume Abella, Jan Andersson, Tullio Vardanega, Francis Vatrinet, Iain Bate, Ian Broster, Mikel Azkarate-askasua, Franck Wartel, Liliana Cucu, Fabrice Cros, Glenn Farrall, Adriana Gogonel, Andrea Gianarro, Benoit Triquet, Carles Hernández, Code Lo, Cristian Maxim, David Morales, Eduardo Quiñones, Enrico Mezzetti, Leonidas Kosmidis, Irune Agirre, Mikel Fernández, Mladen Slijepcevic, Philippa Conmy, Walid Talaboulma:
PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis. DSD 2016: 276-285
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Davide Compagnin, Tullio Vardanega:
An automated framework for the timing analysis of applications for an automotive multicore processor. ETFA 2016: 1-8
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Irune Agirre, Mikel Azkarate-askasua, Asier Larrucea, Jon Pérez, Tullio Vardanega, Francisco J. Cazorla:
Automotive Safety Concept Definition for Mixed-Criticality Integration on a COTS Multicore. SAFECOMP Workshops 2016: 273-285
[c84]
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Enrique Díaz, Jaume Abella, Enrico Mezzetti, Irune Agirre, Mikel Azkarate-askasua, Tullio Vardanega, Francisco J. Cazorla:
Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis. WCET 2016: 1:1-1:11
[c83]
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Leonidas Kosmidis, Davide Compagnin, David Morales, Enrico Mezzetti, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla:
Measurement-Based Timing Analysis of the AURIX Caches. WCET 2016: 9:1-9:11
2015
[j12]
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Enrico Mezzetti, Marco Ziccardi, Tullio Vardanega, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems. Leibniz Trans. Embed. Syst. 2(1): 01:1-01:10 (2015)
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Irune Agirre, Mikel Azkarate-askasua, Asier Larrucea, Jon Pérez, Tullio Vardanega, Francisco J. Cazorla:
A Safety Concept for a Railway Mixed-Criticality Embedded System Based on Multicore Partitioning. CIT/IUCC/DASC/PICom 2015: 1780-1787
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Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla:
Increasing confidence on measurement-based contention bounds for real-time round-robin buses. DAC 2015: 125:1-125:6
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Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla:
Resource usage templates and signatures for COTS multicore processors. DAC 2015: 155:1-155:6
[c79]
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Franck Wartel, Leonidas Kosmidis, Adriana Gogonel, Andrea Baldovin, Zoë R. Stephenson, Benoit Triquet, Eduardo Quiñones, Code Lo, Enrico Mezzetti, Ian Broster, Jaume Abella, Liliana Cucu-Grosjean, Tullio Vardanega, Francisco J. Cazorla:
Timing analysis of an avionics case study on complex hardware/software platforms. DATE 2015: 397-402
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Irune Agirre, Mikel Azkarate-askasua, Carles Hernández, Jaume Abella, Jon Pérez, Tullio Vardanega, Francisco J. Cazorla:
IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis. DSD 2015: 677-684
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Davide Compagnin, Enrico Mezzetti, Tullio Vardanega:
Experimental Evaluation of Optimal Schedulers Based on Partitioned Proportionate Fairness. ECRTS 2015: 115-126
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Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Tullio Vardanega, Francisco J. Cazorla:
Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors. ISORC 2015: 208-217
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Marco Ziccardi, Enrico Mezzetti, Tullio Vardanega, Jaume Abella, Francisco J. Cazorla:
EPC: Extended Path Coverage for Measurement-Based Probabilistic Timing Analysis. RTSS 2015: 338-349
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Marco Ziccardi, Martin Schoeberl, Tullio Vardanega:
A time-composable operating system for the Patmos processor. SAC 2015: 1892-1897
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Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Luca Fossati, Marco Zulianello, Francisco J. Cazorla:
Introduction to partial time composability for COTS multicores. SAC 2015: 1955-1956
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Jaume Abella, Carles Hernández, Eduardo Quiñones, Francisco J. Cazorla, Philippa Ryan Conmy, Mikel Azkarate-askasua, Jon Pérez, Enrico Mezzetti, Tullio Vardanega:
WCET analysis methods: Pitfalls and challenges on their trustworthiness. SIES 2015: 39-48
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Valentino Baraldo, Alberto Zuccato, Tullio Vardanega:
Reconciling Service Orientation with the Cloud. SOSE 2015: 195-202
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Marco Ziccardi, Alessandro Cornaglia, Enrico Mezzetti, Tullio Vardanega:
Software-enforced Interconnect Arbitration for COTS Multicores. WCET 2015: 11-20
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Juan Antonio de la Puente, Tullio Vardanega:
Reliable Software Technologies - Ada-Europe 2015 - 20th Ada-Europe International Conference on Reliable Software Technologies, Madrid Spain, June 22-26, 2015, Proceedings. Lecture Notes in Computer Science 9111, Springer 2015, ISBN 978-3-319-19583-4 [contents]
2014
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Marco Panunzio, Tullio Vardanega:
An architectural approach with separation of concerns to address extra-functional requirements in the development of embedded real-time software systems. J. Syst. Archit. 60(9): 770-781 (2014)
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Marco Panunzio, Tullio Vardanega:
A component-based process with separation of concerns for the development of embedded real-time software systems. J. Syst. Softw. 96: 105-121 (2014)
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Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Ian Broster, Francisco J. Cazorla:
Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture. DSD 2014: 401-410
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Davide Compagnin, Enrico Mezzetti, Tullio Vardanega:
Putting RUN into Practice: Implementation and Evaluation. ECRTS 2014: 75-84
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Jaume Abella, Eduardo Quiñones, Franck Wartel, Tullio Vardanega, Francisco J. Cazorla:
Heart of Gold: Making the Improbable Happen to Increase Confidence in MBPTA. ECRTS 2014: 255-265
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Alberto Zuccato, Tullio Vardanega:
Implementing Elastic Capacity in a Service-Oriented PaaS. ESOCC Workshops 2014: 18-30
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Luca Bonato, Enrico Mezzetti, Tullio Vardanega:
Supporting Global Resource Sharing in RUN-scheduled Multiprocessor Systems. RTNS 2014: 109
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Andrea Baldovin, Geoffrey Nelissen, Tullio Vardanega, Eduardo Tovar:
SPRINT: Extending RUN to Schedule Sporadic Tasks. RTNS 2014: 321
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Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Christine Rochange, Tullio Vardanega, Francisco J. Cazorla:
Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art. WCET 2014: 31-42
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Laurent George, Tullio Vardanega:
Reliable Software Technologies - Ada-Europe 2014, 19th Ada-Europe International Conference on Reliable Software Technologies, Paris, France, June 23-27, 2014. Proceedings. Lecture Notes in Computer Science 8454, Springer 2014, ISBN 978-3-319-08310-0 [contents]
2013
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Francisco J. Cazorla, Eduardo Quiñones, Tullio Vardanega, Liliana Cucu, Benoit Triquet, Guillem Bernat, Emery D. Berger, Jaume Abella, Franck Wartel, Michael Houston, Luca Santinelli, Leonidas Kosmidis, Code Lo, Dorin Maxim:
PROARTIS: Probabilistically Analyzable Real-Time Systems. ACM Trans. Embed. Comput. Syst. 12(2s): 94:1-94:26 (2013)
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Andrea Baldovin, Enrico Mezzetti, Tullio Vardanega:
Towards a Time-Composable Operating System. Ada-Europe 2013: 143-160
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Andrea Baldovin, Enrico Mezzetti, Tullio Vardanega:
Limited preemptive scheduling of non-independent task sets. EMSOFT 2013: 18:1-18:10
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Silvia Mazzini, John M. Favaro, Tullio Vardanega:
Cross-Domain Reuse: Lessons Learned in a Multi-project Trajectory. ICSR 2013: 113-126
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Marco Panunzio, Tullio Vardanega:
On Software Reference Architectures and Their Application to the Space Domain. ICSR 2013: 144-159
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Zoë R. Stephenson, Jaume Abella, Tullio Vardanega:
Supporting industrial use of probabilistic timing analysis with explicit argumentation. INDIN 2013: 734-740
[c57]
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Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla:
Achieving timing composability with measurement-based probabilistic timing analysis. ISORC 2013: 1-8
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Enrico Mezzetti, Tullio Vardanega:
A rapid cache-aware procedure positioning optimization to favor incremental development. IEEE Real-Time and Embedded Technology and Applications Symposium 2013: 107-116
[c55]
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Andrea Baldovin, Andrea Graziano, Enrico Mezzetti, Tullio Vardanega:
Kernel-level time composability for avionics applications. SAC 2013: 1552-1554
[c54]
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Franck Wartel, Leonidas Kosmidis, Code Lo, Benoit Triquet, Eduardo Quiñones, Jaume Abella, Adriana Gogonel, Andrea Baldovin, Enrico Mezzetti, Liliana Cucu, Tullio Vardanega, Francisco J. Cazorla:
Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study. SIES 2013: 241-248
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Francisco J. Cazorla, Tullio Vardanega, Eduardo Quiñones, Jaume Abella:
Upper-bounding Program Execution Time with Extreme Value Theory. WCET 2013: 64-76
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Leonidas Kosmidis, Tullio Vardanega, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
Applying Measurement-Based Probabilistic Timing Analysis to Buffer Resources. WCET 2013: 97-108
2012
[c51]
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Marco Panunzio, Tullio Vardanega:
Ada Ravenscar Code Archetypes for Component-Based Development. Ada-Europe 2012: 1-17
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Patricia López Martínez, Tullio Vardanega:
Handling Synchronization Requirements under Separation of Concerns in Model-Driven Component-Based Development. Ada-Europe 2012: 89-104
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Patricia López Martínez, Tullio Vardanega:
An MDE approach to address synchronization needs in component-based real-time systems. CBSE 2012: 125-134
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Claudio Guidi, Paolo Anedda, Tullio Vardanega:
Towards a New Paas Architecture Generation. CLOSER 2012: 279-282
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Liliana Cucu-Grosjean, Luca Santinelli, Michael Houston, Code Lo, Tullio Vardanega, Leonidas Kosmidis, Jaume Abella, Enrico Mezzetti, Eduardo Quiñones, Francisco J. Cazorla:
Measurement-Based Probabilistic Timing Analysis for Multi-path Programs. ECRTS 2012: 91-101
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Claudio Guidi, Paolo Anedda, Tullio Vardanega:
PaaSSOA: An Open PaaS Architecture for Service Oriented Applications. ESOCC 2012: 208-209
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Antonio Cicchetti, Federico Ciccozzi, Silvia Mazzini, Stefano Puri, Marco Panunzio, Alessandro Zovi, Tullio Vardanega:
CHESS: a model-driven engineering tool environment for aiding the development of complex industrial systems. ASE 2012: 362-365
[c44]
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Andrea Baldovin, Enrico Mezzetti, Tullio Vardanega:
A Time-composable Operating System. WCET 2012: 69-80
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Tullio Vardanega:
12th International Workshop on Worst-Case Execution Time Analysis, WCET 2012, July 10, 2012, Pisa, Italy. OASIcs 23, Schloss Dagstuhl - Leibniz-Zentrum für Informatik 2012, ISBN 978-3-939897-41-5 [contents]
2011
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Marco Panunzio, Tullio Vardanega:
Pitfalls and misconceptions in component-oriented approaches for real-time embedded systems: lessons learned and solutions. SIGBED Rev. 8(1): 6-13 (2011)
[c43]
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Giovanni Giacobbi, Tullio Vardanega:
Measuring I/O Performance in Xen Paravirtualization Virtual Machines. CLOSER 2011: 656-662
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Alexander B. Romanovsky, Tullio Vardanega:
Reliable Software Technologies - Ada-Europe 2011 - 16th Ada-Europe International Conference on Reliable Software Technologies, Edinburgh, UK, June 20-24, 2011. Proceedings. Lecture Notes in Computer Science 6652, Springer 2011, ISBN 978-3-642-21337-3 [contents]
2010
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Daniela Cancila, Roberto Passerone, Tullio Vardanega, Marco Panunzio:
Ensuring Correctness in the Specification and Handling of Non-Functional Attributes in High-Integrity Real-Time Embedded Systems. IEEE Trans. Ind. Informatics 6(2): 181-194 (2010)
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Enrico Mezzetti, Adam Betts, José F. Ruiz, Tullio Vardanega:
Cache-Aware Development of High-Integrity Systems. Ada-Europe 2010: 139-152
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Enrico Mezzetti, Marco Panunzio, Tullio Vardanega:
Preservation of Timing Properties with the Ada Ravenscar Profile. Ada-Europe 2010: 153-166
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Marco Panunzio, Tullio Vardanega:
A Component Model for On-board Software Applications. EUROMICRO-SEAA 2010: 57-64
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Enrico Mezzetti, Tullio Vardanega:
Towards a Cache-Aware Development of High Integrity Real-Time Systems. RTCSA 2010: 329-338
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Enrico Mezzetti, Marco Panunzio, Tullio Vardanega:
Bounding the Effects of Resource Access Protocols on Cache Behavior. WCET 2010: 11-22
[c37]
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Alessandro Maccagnan, Tullio Vardanega, Erika Feltrin, Giorgio Valle, Mauro Riva, Nicola Cannata:
A Multi-Agent System for the Automated Handling of Experimental Protocols in Biological Laboratories. WOA 2010
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Jorge Real, Tullio Vardanega:
Reliable Software Technologiey - Ada-Europe 2010, 15th Ada-Europe International Conference on Reliable Software Technologies, Valencia, Spain, June 14-18, 2010. Proceedings. Lecture Notes in Computer Science 6106, Springer 2010, ISBN 978-3-642-13549-1 [contents]

2000 – 2009

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What is the meaning of the colors in the publication lists?

2009
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Alessandro Zovi, Tullio Vardanega:
Requirements on the Target Programming Language for High-Integrity MDE. Ada-Europe 2009: 1-15
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Silvia Mazzini, Stefano Puri, Tullio Vardanega:
An MDE methodology for the development of high-integrity real-time systems. DATE 2009: 1154-1159
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Tullio Vardanega:
Property Preservation and Composition with Guarantees: From ASSERT to CHESS. ISORC 2009: 125-132
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Marco Panunzio, Tullio Vardanega:
On Component-Based Development and High-Integrity Real-Time Systems. RTCSA 2009: 79-84
2008
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Matteo Bordin, Marco Panunzio, Tullio Vardanega:
Fitting Schedulability Analysis Theory into Model-Driven Engineering. ECRTS 2008: 135-144
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Fabrice Kordon, Tullio Vardanega:
Reliable Software Technologies - Ada-Europe 2008, 13th Ada-Europe International Conference on Reliable Software Technologies, Venice, Italy, June 16-20, 2008. Proceedings. Lecture Notes in Computer Science 5026, Springer 2008, ISBN 978-3-540-68621-7 [contents]
2007
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Matteo Bordin, Tullio Vardanega:
Correctness by Construction for High-Integrity Real-Time Systems: A Metamodel-Driven Approach. Ada-Europe 2007: 114-127
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Marco Panunzio, Tullio Vardanega:
A Metamodel-Driven Process Featuring Advanced Model-Based Timing Analysis. Ada-Europe 2007: 128-141
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Tullio Vardanega, José F. Ruiz:
Introduction. IRTAW 2007: 15-17
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José Antonio Pulido, Juan Antonio de la Puente, Jérôme Hugues, Matteo Bordin, Tullio Vardanega:
Ada 2005 code patterns for metamodel-based code generation. IRTAW 2007: 53-58
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Matteo Bordin, Tullio Vardanega:
Real-time Java from an automated code generation perspective. JTRES 2007: 63-72
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Marco Panunzio, Tullio Vardanega:
An Approach to the Timing Analysis of Hierarchical Systems. RTCSA 2007: 157-164
2006
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José Antonio Pulido, Santiago Urueña, Juan Zamorano, Tullio Vardanega, Juan Antonio de la Puente:
Hierarchical Scheduling with Ada 2005. Ada-Europe 2006: 1-12
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Vaclav Cechticky, Martin Egli, Alessandro Pasetti, O. Rohlik, Tullio Vardanega:
A UML2 Profile for Reusable and Verifiable Software Components for Real-Time Applications. ICSR 2006: 312-325
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Tullio Vardanega:
Property-Preserving Reuse-Geared Approach to Model-Driven Development. RTCSA 2006: 223-232
2005
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Tullio Vardanega, Juan Zamorano, Juan Antonio de la Puente:
On the Dynamic Semantics and the Timing Behavior of Ravenscar Kernels. Real Time Syst. 29(1): 59-89 (2005)
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Matteo Bordin, Tullio Vardanega:
A New Strategy for the HRT-HOOD to Ada Mapping. Ada-Europe 2005: 51-66
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Matteo Bordin, Tullio Vardanega:
Automated Model-Based Generation of Ravenscar-Compliant Source Code. ECRTS 2005: 59-67
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Tullio Vardanega, Andy J. Wellings:
Reliable Software Technology - Ada-Europe 2005, 10th Ada-Europe International Conference on Reliable Software Technologies, York, UK, June 20-24, 2005, Proceedings. Lecture Notes in Computer Science 3555, Springer 2005, ISBN 3-540-26286-5 [contents]
2004
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Tullio Vardanega, Marco Di Natale, Silvia Mazzini, Massimo D'Alessandro:
Component-Based Real-Time Design: Mapping HRT-HOOD to UML. EUROMICRO 2004: 6-13
2003
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Silvia Mazzini, Massimo D'Alessandro, Marco Di Natale, Andrea Domenici, Giuseppe Lipari, Tullio Vardanega:
HRT-UML: Taking HRT-HOOD onto UML. Ada-Europe 2003: 405-416
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Silvia Mazzini, Massimo D'Alessandro, Marco Di Natale, Giuseppe Lipari, Tullio Vardanega:
Issues in Mapping HRT-HOOD to UML. ECRTS 2003: 221-228
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Michael González Harbour, Tullio Vardanega:
Report of session: current real-time AIs. IRTAW 2003: 22-23
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Alan Burns, Andy J. Wellings, Tullio Vardanega:
Report of session: flexible scheduling in Ada. IRTAW 2003: 32-35
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Tullio Vardanega:
Ravenscar design patterns?: reflections on use of the Ravenscar profile. IRTAW 2003: 65-73
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Alan Burns, Tullio Vardanega:
Report of session: generating new AIs. IRTAW 2003: 93-95
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Tullio Vardanega, Luís Miguel Pinho:
Session summary: the future of IRTAW. IRTAW 2003: 96
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Tullio Vardanega:
Proceedings of the 12th International Workshop on Real-Time Ada, IRTAW 2003, Viana do Castelo, Portugal, September 15-19, 2003. ACM 2003, ISBN 978-1-4503-7446-0 [contents]
2002
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Tullio Vardanega, Gert Caspersen:
Engineering software reuse for on-board embedded real-time systems. Softw. Pract. Exp. 32(3): 233-264 (2002)
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Alejandro Alonso, Roberto López, Tullio Vardanega, Juan Antonio de la Puente:
Using Object Orientation in High Integrity Applications: A Case Study. Ada-Europe 2002: 357-366
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Andy J. Wellings, Tullio Vardanega:
Report of session: language changes for scheduling, modeling and analysis. IRTAW 2002: 125-127
2001
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Tullio Vardanega, Rodrigo García, Juan Antonio de la Puente:
An Application Case for Ravenscar Technology: Porting OBOSS to GNAT/ORK. Ada-Europe 2001: 392-404
2000
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Brian Dobbing, Tullio Vardanega:
Report of session: analysis of the J consortium real-time Java proposal. IRTAW 2000: 17-18
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Tullio Vardanega, Gert Caspersen:
Using the Ravenscar profile for space applications: the OBOSS case. IRTAW 2000: 96-104

1990 – 1999

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1999
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Tullio Vardanega:
On the Distribution of Control Functions in New-Generation On-Board Embedded Real-Time Systems. Parallel Distributed Comput. Pract. 2(1) (1999)
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Tullio Vardanega, Jan van Katwijk:
A Software Process for the Construction of Predictable On-Board Embedded Real-Time Systems. Softw. Pract. Exp. 29(3): 235-266 (1999)
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Tullio Vardanega, Gert Caspersen, Jan Storbank Pedersen:
A Case Study in the Reuse of On-board Embedded Real-Time Software. Ada-Europe 1999: 425-436
1998
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Tullio Vardanega:
On the Construction of New-Generation On-Board Real-Time Systems. Integr. Comput. Aided Eng. 5(3): 227-244 (1998)
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Tullio Vardanega, Jan van Katwijk:
Productive engineering of predictable embedded real-time systems: the road to maturity. Inf. Softw. Technol. 40(13): 745-764 (1998)
1997
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Alan Burns, Ted Baker, Tullio Vardanega:
Tasking profiles (session summary). IRTAW 1997: 5-7
1996
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Tullio Vardanega:
Tool support for the construction of statically analysable hard real-time Ada systems. RTSS 1996: 129-135
1995
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Tullio Vardanega, P. David, J.-F. Chane, Wolfgang R. Mader, R. Messaros, Jean Arlat:
On the Development of Fault-Tolerant On-Board Control Software and its Evaluation by Fault Injection. FTCS 1995: 510-515
1994
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Tullio Vardanega:
Experience with the Development of Hard Real-Time Embedded Ada Software. ICSE 1994: 301-308
1993
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C. M. Bailey, E. Fyfe, Tullio Vardanega, Andy J. Wellings:
The use of preemptive priority-based scheduling for space applications. RTSS 1993: 253-257
1991
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Tullio Vardanega:
An operating system suited for integrated broadband communications networks. LCN 1991: 429-441

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