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Robert Lo
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2020 – today
- 2024
- [c3]Jing Yu Koh, Robert Lo, Lawrence Jang, Vikram Duvvur, Ming Chong Lim, Po-Yu Huang, Graham Neubig, Shuyan Zhou, Russ Salakhutdinov, Daniel Fried:
VisualWebArena: Evaluating Multimodal Agents on Realistic Visual Web Tasks. ACL (1) 2024: 881-905 - [c2]Shuyan Zhou, Frank F. Xu, Hao Zhu, Xuhui Zhou, Robert Lo, Abishek Sridhar, Xianyi Cheng, Tianyue Ou, Yonatan Bisk, Daniel Fried, Uri Alon, Graham Neubig:
WebArena: A Realistic Web Environment for Building Autonomous Agents. ICLR 2024 - [i6]Jing Yu Koh, Robert Lo, Lawrence Jang, Vikram Duvvur, Ming Chong Lim, Po-Yu Huang, Graham Neubig, Shuyan Zhou, Ruslan Salakhutdinov, Daniel Fried:
VisualWebArena: Evaluating Multimodal Agents on Realistic Visual Web Tasks. CoRR abs/2401.13649 (2024) - [i5]Tianyue Ou, Frank F. Xu, Aman Madaan, Jiarui Liu, Robert Lo, Abishek Sridhar, Sudipta Sengupta, Dan Roth, Graham Neubig, Shuyan Zhou:
Synatra: Turning Indirect Knowledge into Direct Demonstrations for Digital Agents at Scale. CoRR abs/2409.15637 (2024) - 2023
- [c1]Robert Lo, Abishek Sridhar, Frank F. Xu, Hao Zhu, Shuyan Zhou:
Hierarchical Prompting Assists Large Language Model on Web Navigation. EMNLP (Findings) 2023: 10217-10244 - [i4]Abishek Sridhar, Robert Lo, Frank F. Xu, Hao Zhu, Shuyan Zhou:
Hierarchical Prompting Assists Large Language Model on Web Navigation. CoRR abs/2305.14257 (2023) - [i3]Robert Lo, Arnhav Datar, Abishek Sridhar:
LIC-GAN: Language Information Conditioned Graph Generative GAN Model. CoRR abs/2306.01937 (2023) - [i2]Andrew Stange, Robert Lo, Abishek Sridhar, Kousik Rajesh:
Exploring the Role of the Bottleneck in Slot-Based Models Through Covariance Regularization. CoRR abs/2306.02577 (2023) - [i1]Shuyan Zhou, Frank F. Xu, Hao Zhu, Xuhui Zhou, Robert Lo, Abishek Sridhar, Xianyi Cheng, Yonatan Bisk, Daniel Fried, Uri Alon, Graham Neubig:
WebArena: A Realistic Web Environment for Building Autonomous Agents. CoRR abs/2307.13854 (2023)
2010 – 2019
- 2012
- [j1]Jui-Jen Wu, Meng-Fan Chang, Shau-Wei Lu, Robert Lo, Quincy Li:
A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances. IEEE Trans. Circuits Syst. II Express Briefs 59-II(11): 790-794 (2012)
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