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2020 – today
- 2024
[j21]Zenghong Wu, Kun Zhang, Weijun Wang, Mengke Fan, Rong Lin:
The differences in gastric cancer epidemiological data between SEER and GBD: a joinpoint and age-period-cohort analysis. J. Big Data 11(1): 51 (2024)- 2023
- [i1]Rong Lin, Zhekai Luo, Jiansen He, Lun Xie, Chuanpeng Hou, Shuwei Chen:
Prediction of solar wind speed by applying convolutional neural network to potential field source surface (PFSS) magnetograms. CoRR abs/2304.01234 (2023) - 2022
- [c36]Rong Lin:
Research on the precise employment model of college students from the perspective of competency. CIS 2022: 289-291 - 2021
- [c35]Rong Lin, Chun-Yang Zhang:
Contrastive Learning Framework by Maximizing Mutual Information for Visual Question Answering. SPAC 2021: 483-488 - 2020
- [c34]Rong Lin, Zhiyong Wei, Yunfei Chen
:
Effects of Commensurability on the Friction and Energy Dissipation in Graphene/Graphene Interface. NEMS 2020: 524-528
2010 – 2019
- 2016
- [c33]Ping Hu, Shi Peng, Chengmin Wang, Huicong Fan, Rong Lin, Yong Liu:
Application research of the power line carrier communication multiband based on G3 technology. ICSAI 2016: 814-818
2000 – 2009
- 2005
- [c32]Kendra M. L. Cooper, João W. Cangussu, Rong Lin, Ganesan Sankaranarayanan, Ragouramane Soundararadjane, W. Eric Wong:
An Empirical Study on the Specification and Selection of Components Using Fuzzy Logic. CBSE 2005: 155-170 - 2003
- [j20]Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya:
An Efficient Parallel Prefix Sums Architecture with Domino Logic. IEEE Trans. Parallel Distributed Syst. 14(9): 922-931 (2003) - [c31]Rong Lin:
A Reconfigurable Low-Power High-Performance Matrix Multiplier Architecture with Borrow Parallel Counters. IPDPS 2003: 182 - 2002
- [j19]Rong Lin, Stephan Olariu:
Fast Inner Product Computation on Short Buses. VLSI Design 14(4): 337-347 (2002) - [c30]Rong Lin, Martin Margala:
Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor. ACM Great Lakes Symposium on VLSI 2002: 172-177 - [c29]Rong Lin:
Bit-Matrix Decomposition and Dynamic Reconfiguration: A Unified Arithmetic Processor Architecture, Design and Test. IPDPS 2002 - 2001
- [j18]Rong Lin:
Reconfigurable parallel inner product processor architectures. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 261-272 (2001) - [j17]Rong Lin:
A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits. VLSI Design 12(3): 377-390 (2001) - [c28]Rong Lin:
Inner Product Processor Designs Using High-Performance, Non-Binary Logic Circuits. PDCS 2001: 345-350 - [c27]Rong Lin:
A run-time reconfigurable array of multipliers architecture. IPDPS 2001: 143 - [c26]Rong Lin:
Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design. ISQED 2001: 325-330 - 2000
- [j16]Rong Lin, Koji Nakano, Stephan Olariu, Maria Cristina Pinotti, James L. Schwing, Albert Y. Zomaya:
Scalable Hardware-Algorithms for Binary Prefix Sums. IEEE Trans. Parallel Distributed Syst. 11(8): 838-850 (2000) - [c25]Rong Lin:
Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme. EUROMICRO 2000: 2456-2463 - [c24]Rong Lin, James L. Schwing:
A Non-binary Parallel Arithmetic Architecture. IPDPS Workshops 2000: 149-154 - [c23]Rong Lin:
A Reconfigurable Low-Power High-Performance Matrix Multiplier Design. ISQED 2000: 321-328
1990 – 1999
- 1999
- [j15]Rong Lin, Stephan Olariu, James L. Schwing, Biing-Feng Wang:
The Mesh with Hybrid Buses: An Efficient Parallel Architecture for Digital Geometry. IEEE Trans. Parallel Distributed Syst. 10(3): 266-280 (1999) - [j14]Rong Lin, Stephan Olariu:
Efficient VLSI architectures for Columnsort. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 135-138 (1999) - [j13]Rong Lin, Stephan Olariu:
Reconfigurable Shift Switching Parallel Comparators. VLSI Design 9(1): 83-90 (1999) - [j12]Stephan Olariu, Rong Lin:
Guest Editorial. VLSI Design 9(1) (1999) - [c22]Rong Lin, Kevin E. Kerr, André S. Botha:
A Novel Approach for CMOS Parallel Counter Design. EUROMICRO 1999: 1112-1119 - [c21]Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya:
An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic. IPPS/SPDP 1999: 273-277 - [c20]Rong Lin, Koji Nakano, Stephan Olariu, Maria Cristina Pinotti, James L. Schwing, Albert Y. Zomaya:
Scalable Hardware-Algorithms for Binary Prefix Sums. IPPS/SPDP Workshops 1999: 634-642 - 1998
- [j11]Rong Lin, Stephan Olariu:
A Fast Parallel Algorithm to Recognize P4-sparse Graphs. Discret. Appl. Math. 81(1-3): 191-215 (1998) - [c19]Rong Lin, Koji Nakano, Stephan Olariu, Maria Cristina Pinotti, James L. Schwing, Albert Y. Zomaya:
A Scalable VLSI Architecture for Binary Prefix Sums. IPPS/SPDP 1998: 333-337 - 1997
- [c18]Rong Lin:
Fast multiplier schemes using large parallel counters and shift switches. HiPC 1997: 302-308 - [c17]Rong Lin:
Reconfigurable buses with shift switches for fast final additions of parallel multipliers. PDPTA 1997: 513-521 - 1995
- [j10]Rong Lin, Stephan Olariu:
A Cost-optimal Erew Breadth-first Algorithm for Ordered Trees, with Applications. Parallel Algorithms Appl. 5(3-4): 187-197 (1995) - [j9]Rong Lin, Stephan Olariu:
Reconfigurable Buses with Shift Switching: Concepts and Applications. IEEE Trans. Parallel Distributed Syst. 6(1): 93-102 (1995) - [c16]Rong Lin, Stephan Olariu:
A simple array processor for binary prefix sums. ASAP 1995: 113- - 1994
- [j8]Rong Lin, Stephan Olariu:
An Optimal Parallel Matching Algorithm for Cographs. J. Parallel Distributed Comput. 22(1): 26-36 (1994) - [j7]Rong Lin, Stephan Olariu, James L. Schwing, Jingyuan Zhang:
An Efficient Erew Algorithm for Minimum Path Cover and Hamiltonicity on Cographs. Parallel Algorithms Appl. 2(1-2): 99-113 (1994) - [j6]Rong Lin, Stephan Olariu, James L. Schwing, Jingyuan Zhang:
Computing on Reconfigurable Buses - A New Computational Paradigm. Parallel Process. Lett. 4: 465-476 (1994) - [c15]Rong Lin, Stephan Olariu, James L. Schwing:
An efficient VLSI architecture for digital geometry. ASAP 1994: 392-403 - [c14]Rong Lin:
Convolution Computation on Shift Switching Buses. HICSS (2) 1994: 120-129 - [c13]Dharmavani Bhagavathi, Venkatavasu Bokka, Himabindu Gurla, Rong Lin, Stephan Olariu, James L. Schwing, W. Shen, Larry Wilson:
Time-Optimal Multiple Rank Computations on Meshes with Multiple Broadcasting. ICPP (3) 1994: 35-38 - [c12]Rong Lin, Stephan Olariu:
Application-specific array processors for binary prefix sum computation. SPDP 1994: 118-125 - 1993
- [j5]Rong Lin, Stephan Olariu, James L. Schwing, Jingyuan Zhang:
Simulating Enhanced Meshes, with Applications. Parallel Process. Lett. 3: 59-70 (1993) - [c11]Rong Lin, Stephan Olariu:
A practical constant time sorting network. ASAP 1993: 380-391 - [c10]Dharmavani Bhagavathi, Himabindu Gurla, Stephan Olariu, Rong Lin, James L. Schwing, Jingyuan Zhang:
Square Meshes Are Not Optimal For Convex Hull Computation. ICPP (3) 1993: 307-310 - 1992
- [j4]Rong Lin, Stephan Olariu:
A fast cost-optimal parallel algorithm for the lowest common ancestor problem. Parallel Comput. 18(5): 511-516 (1992) - [c9]Rong Lin, Stephan Olariu:
Computing the Inner Product on Reconfigurable Buses with Shift Switching. CONPAR 1992: 181-192 - [c8]Rong Lin:
Reconfigurable Buses with Shift Switching - VLSI RADIX Sort. ICPP (3) 1992: 2-9 - 1991
- [j3]Rong Lin:
Fast Algorithms for Lowest Common Ancestors on a Processor Array with Reconfigurable Buses. Inf. Process. Lett. 40(4): 223-230 (1991) - [j2]Rong Lin, Stephan Olariu:
An NC Recognition Algorithm for Cographs. J. Parallel Distributed Comput. 13(1): 76-90 (1991) - [c7]Rong Lin, Stephan Olariu:
Optimal parallel coloring algorithms for a family of tree-representable graphs. ACM Conference on Computer Science 1991: 29-38 - [c6]Rong Lin, Stephan Olariu:
A Simple Optimal Parallel Algorithm to Solve the Lowest Common Ancestor Problem. ICCI 1991: 455-461 - [c5]Rong Lin, Stephan Olariu:
A Fast Parallel Algorithm to Compute Path Functions for Cographs. ICPP (3) 1991: 263-266 - [c4]Rong Lin, Stephan Olariu:
An optimal parallel matching algorithm for cographs. SPDP 1991: 759-766 - 1990
- [j1]Rong Lin, Stephan Olariu:
A Fast Parallel, Algorithm to Recognize, Partitionable Graphs. Inf. Process. Lett. 36(3): 153-157 (1990) - [c3]Rong Lin, Stephan Olariu:
Fast Parallel Algorithms for Cographs. FSTTCS 1990: 176-189 - [c2]Rong Lin, Stephan Olariu:
A fast NC algorithm to recognize P4-reducible graphs. Jerusalem Conference on Information Technology 1990: 402-413 - [c1]Rong Lin, Stephan Olariu:
On the parallel recognition of some tree-representable graphs. SPDP 1990: 6-13
1980 – 1989
- 1989
- [b1]Rong Lin:
A Classification Approach for Automated Reasoning Systems-A Case Study in Graph Theory. Old Dominion University, Norfolk, Virginia, USA, 1989
Coauthor Index
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