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2010 – 2019
- 2019
[i1]Lois Orosa, Yaohua Wang, Ivan Puddu, Mohammad Sadrosadati, Kaveh Razavi, Juan Gómez-Luna, Hasan Hassan, Nika Mansouri-Ghiasi, Arash Tavakkol, Minesh Patel, Jeremie S. Kim, Vivek Seshadri, Uksong Kang, Saugata Ghose, Rodolfo Azevedo, Onur Mutlu:
Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices. CoRR abs/1902.07344 (2019)- 2016
- [c4]Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jaewook Lee, Uksong Kang, Young-Soo Sohn, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Gyo-Young Jin:
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution. ISSCC 2016: 316-317 - [c3]Krishna T. Malladi, Uksong Kang, Manu Awasthi, Hongzhong Zheng:
DRAMScale: Mechanisms to Increase DRAM Capacity. MEMSYS 2016: 325-326 - 2010
- [j2]Uksong Kang, Hoeju Chung, Seongmoo Heo, Dukha Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Dong Hyeon Jang, Nam-Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Yoo, Joo-Sun Choi, Changhyun Kim, Young-Hyun Jun:
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. IEEE J. Solid State Circuits 45(1): 111-119 (2010)
2000 – 2009
- 2009
- [c2]Uksong Kang, Hoeju Chung, Seongmoo Heo, Soon-Hong Ahn, Hoon Lee, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jin Ho Kim, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae Lee, Tae-Kyung Jung, Jei-Hwan Yoo, Changhyun Kim:
8Gb 3D DDR3 DRAM using through-silicon-via technology. ISSCC 2009: 130-131 - 2007
- [j1]Kyu-Hyoun Kim
, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim:
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. IEEE J. Solid State Circuits 42(1): 193-200 (2007) - 2006
- [c1]Kyu-Hyoun Kim, Uksong Kang, Hoeju Chung, Dukha Park, Woo-Seop Kim, Young-Chan Jang, Moon-Sook Park, Hoon Lee, Jinyoung Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jae-Kwan Kim, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo-Sun Choi, Changhyun Kim:
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. ISSCC 2006: 527-536
Coauthor Index
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