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2020 – today
- 2024
[c76]Liang-Ying Su, Shih-Hsu Huang:
Design Flow for Incorporating Camouflaged Logic Gates to Enhance Hardware Security While Considering Timing Closure. ISCAS 2024: 1-5- 2023
- [c75]Shih-Hsu Huang, Wei-Che Cheng, Jin-Fu Li:
Hardware Trojans of Computing-In-Memories: Issues and Methods. DFT 2023: 1-6 - [c74]Liang-Ying Su, Shih-Hsu Huang:
A Metal-Only ECO Algorithm for Improving Hardware Security with Gate Camouflaging. ICCE-Taiwan 2023: 301-302 - [c73]Hsin-Chen Lu, Shih-Hsu Huang:
Fault-Tolerant Near-Memory MAC Design with Redundant Memories. ICCE-Taiwan 2023: 303-304 - [c72]Chia-Jo Lin, Shih-Hsu Huang, Wan-Yi Hsueh, Wei-Chung Hsu, Chih-Wen Su:
An Automatic Facial Analysis System for The Detection of Pediatric Obstructive Sleep Apnea. ICCE-Taiwan 2023: 309-310 - [c71]Meng-Shan Wu, Yen-Lin Chua, Jin-Fu Li, Yun-Ting Chuan, Shih-Hsu Huang:
Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. ITC-Asia 2023: 1-6 - 2022
- [c70]Hsu-Yu Kao, Shih-Hsu Huang:
A Behavior-Level Simulation Framework for RRAM-Based Deep Learning Accelerators with Flexible Architecture Configurations. AICAS 2022: 166-169 - [c69]Bo-Xi Lai, Shih-Hsu Huang, Hsu-Yu Kao:
A Reinforcement Learning Methodology for The Search of SRAM CIM-based Accelerator Configuration. ICCE-TW 2022: 141-142 - [c68]De-Yang Chiu, Shih-Hsu Huang:
Network Pruning by Feature Map Sharing with K-Means Clustering. ICCE-TW 2022: 143-144 - [c67]Chuan-Han Cheng, Shih-Hsu Huang, Jin-Fu Li:
Design and Dataflow for Multibit SRAM-Based MAC Operations. ISOCC 2022: 159-160 - [c66]De-Yang Chiu, Shih-Hsu Huang:
Dataflow and Hardware Design for The Sharing of Feature Maps. ISOCC 2022: 175-176 - 2021
- [j33]Hsu-Yu Kao
, Xin-Jia Chen, Shih-Hsu Huang:
Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing. Sensors 21(15): 5081 (2021) - [j32]Yui-Kai Weng, Shih-Hsu Huang, Hsu-Yu Kao:
Block-Based Compression and Corresponding Hardware Circuits for Sparse Activations. Sensors 21(22): 7468 (2021) - [c65]Yi-Liang Hong, Yui-Kai Weng, Shih-Hsu Huang:
Hardware Implementation for Fending off Side-Channel Attacks. ICCE-TW 2021: 1-2 - [c64]Yui-Kai Weng, Shih-Hsu Huang, Hsu-Yu Kao:
Block-Based Compression for Reducing Indexing Cost of DNN Accelerators. ICCE-TW 2021: 1-2 - [c63]En-Hui Zhang, Shih-Hsu Huang:
Low-Power Low-Error Fixed-Width Multiplier Design for Digital Signal Processing. ICCE 2021: 1-5 - [c62]Wei-Hung Lin, Hsu-Yu Kao, Shih-Hsu Huang:
Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators. ISOCC 2021: 282-283 - [c61]Jia-Xiang Tang, Shih-Hsu Huang, Jui-Hung Hung:
ECO Timing Optimization with Data Paths and Clock Paths Considered. ISPACS 2021: 1-2 - 2020
- [j31]Che-Wei Tung, Shih-Hsu Huang:
A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations Into Partial Product Reduction Process. IEEE Access 8: 87367-87377 (2020) - [c60]Xin-Jia Chen, Shih-Hsu Huang:
Low-Power Small-Area $3\times 3$ Convolution Hardware Design. ICCE-TW 2020: 1-2 - [c59]Shi-Rou Lin, Wei-Hung Lin, Shih-Hsu Huang, Chun-Lung Hsu, Chi-Tien Sun:
Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design. ICCE-TW 2020: 1-2 - [c58]Yu-Hsuan Wu, Wei-Hung Lin, Shih-Hsu Huang:
Low-Power Hardware Implementation for Parametric Rectified Linear Unit Function. ICCE-TW 2020: 1-2 - [c57]En-Hui Zhang, Shih-Hsu Huang:
A Simple Yet Accurate Method for The Unsigned Fixed-Width Multiplier Design. ICCE-TW 2020: 1-2 - [c56]Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng:
Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. VTS 2020: 1-6
2010 – 2019
- 2019
- [c55]Fan-Hsuan Tang, Hsu-Yu Kao, Shih-Hsu Huang, Jin-Fu Li:
3D Test Wrapper Chain Optimization with I/O Cells Binding Considered. 3DIC 2019: 1-4 - [c54]Wei-Hsuan Yang, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun, Shih-Hsu Huang:
A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. 3DIC 2019: 1-3 - [c53]Po-Chieh Chang, Shih-Hsu Huang:
IC Camouflaging by Using Universal Gates under Timing Constraints. ICCE-TW 2019: 1-2 - [c52]Chih-Hsiang Chang, Hsu-Yu Kao, Shih-Hsu Huang:
Hardware Implementation for Multiple Activation Functions. ICCE-TW 2019: 1-2 - [c51]Chih-Hsiang Chang, En-Hui Zhang, Shih-Hsu Huang:
Softsign Function Hardware Implementation Using Piecewise Linear Approximation. ISPACS 2019: 1-2 - [c50]Wei-Hung Lin, Hsu-Yu Kao, Shih-Hsu Huang:
A Design Framework for Hardware Approximation of Deep Neural Networks. ISPACS 2019: 1-2 - 2018
- [c49]Chen-Hsien Lin, Shih-Hsu Huang, Wei-Kai Cheng:
An Effective Approach for Building Low-Power General Activity-Driven Clock Trees. ISOCC 2018: 13-14 - [c48]Wei-Kai Cheng, Jian-Kai Chen, Shih-Hsu Huang:
Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction. ISOCC 2018: 50-51 - [c47]Shih-Hsu Huang:
Keynote Talk: 3D Core-based SoC Testing for Low Power and TSV Count Minimization. NoCArc@MICRO 2018: 1 - [c46]Yu-Yi Wu, Shih-Hsu Huang:
TSV-aware 3D test wrapper chain optimization. VLSI-DAT 2018: 1-4 - 2017
- [j30]Chung-Han Chou, Yenting Lai, Yi-Chun Chang, Chih-Yu Wang, Liang-Chia Cheng, Shih-Hsu Huang, Shih-Chieh Chang:
Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 146-155 (2017) - [c45]Yen-Chun Ko, Shih-Hsu Huang:
3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints. ATS 2017: 260-265 - [c44]Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake:
Overview of the 2017 CAD contest at ICCAD: Invited paper. ICCAD 2017: 855-856 - 2016
- [j29]Shih-Hsu Huang, Chun-Hua Cheng:
Power-mode-aware buffer synthesis for low-power clock skew minimization. IEICE Electron. Express 13(14): 20160511 (2016) - [j28]Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang:
Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1189-1192 (2016) - [c43]Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake:
Overview of the 2016 CAD contest at ICCAD. ICCAD 2016: 38 - [c42]Te-Jui Wang, Shih-Hsu Huang, Wei-Kai Cheng, Yih-Chih Chou:
Top-level activity-driven clock tree synthesis with clock skew variation considered. ISCAS 2016: 2591-2594 - 2015
- [j27]Shih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh:
Clock Period Minimization with Minimum Leakage Power. ACM Trans. Design Autom. Electr. Syst. 21(1): 9:1-9:33 (2015) - [c41]Natarajan Viswanathan, Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim:
Overview of the 2015 CAD Contest at ICCAD. ICCAD 2015: 910-911 - 2014
- [j26]Shih-Hsu Huang, Hua-Hsin Yeh:
Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(8): 1699-1708 (2014) - [c40]Hua-Hsin Yeh, Chun-Hua Cheng, Shih-Hsu Huang:
Live demonstration: A low-power high-level synthesis system. APCCAS 2014: 165-166 - [c39]Tsung-Tang Lin, Wen-Pin Tu, Shih-Hsu Huang:
Self-adjusting mechanism to dynamically suppress the effect of PVT variations on clock skew. APCCAS 2014: 308-311 - [c38]Hua-Hsin Yeh, Wen-Pin Tu, Jian-Zhi Shen, Tung-Hua Yen, Shih-Hsu Huang:
Abstract bus interface unit for ESL design from TLM 2.0 communications to the real bus protocol. APCCAS 2014: 611-614 - [c37]Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh:
Leakage-power-aware clock period minimization. DATE 2014: 1-6 - 2013
- [j25]Shih-Hsu Huang, Wen-Pin Tu, Chia-Ming Chang, Song-Bin Pan:
Low-power anti-aging zero skew clock gating. ACM Trans. Design Autom. Electr. Syst. 18(2): 27:1-27:37 (2013) - [c36]Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng:
Co-synthesis of data paths and clock control paths for minimum-period clock gating. DATE 2013: 1831-1836 - [c35]Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou:
Low-power timing closure methodology for ultra-low voltage designs. ICCAD 2013: 697-704 - 2012
- [j24]Shih-Hsu Huang, Wen-Pin Tu, Bing-Hung Li:
High-Level Synthesis for Minimum-Area Low-Power Clock Gating. J. Inf. Sci. Eng. 28(5): 971-988 (2012) - [c34]Chun-Hua Cheng, Wei-Shuo Tzeng, Shih-Hsu Huang:
Simultaneous wafer bonding type selection and layer assignment for TSV count minimization. APCCAS 2012: 627-630 - [c33]Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng:
Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. ASP-DAC 2012: 245-250 - [c32]Wen-Pin Tu, Shih-Wei Wu, Shih-Hsu Huang, Mely Chen Chi:
NBTI-aware dual threshold voltage assignment for leakage power reduction. ISCAS 2012: 349-352 - [c31]Hua-Hsin Yeh, Shih-Hsu Huang, Chun-Hua Cheng:
A formal approach to slack-driven high-level synthesis. ISCAS 2012: 584-587 - 2011
- [j23]Shih-Hsu Huang, Guan-Yu Jhuo, Wei-Lun Huang:
Minimum Inserted Buffers for Clock Period Minimization. J. Inf. Sci. Eng. 27(5): 1513-1526 (2011) - [j22]Chih-Hung Lee, Shih-Hsu Huang, Chun-Hua Cheng:
Accurate TSV Number Minimization in High-Level Synthesis. J. Inf. Sci. Eng. 27(5): 1527-1543 (2011) - [c30]Shih-Hsu Huang, Wen-Pin Tu, Hua-Hsin Yeh, Chun-Hua Cheng:
Teaching three-dimensional system-in-package design automation in a semester course. MSE 2011: 52-55 - [c29]Wen-Pin Tu, Yen-Hsin Lee, Shih-Hsu Huang:
TSV sharing through multiplexing for TSV count minimization in high-level synthesis. SoCC 2011: 156-159 - 2010
- [j21]Shih-Hsu Huang, Chun-Hua Cheng:
Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization. J. Inf. Sci. Eng. 26(6): 2249-2266 (2010) - [c28]Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan:
Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. ASP-DAC 2010: 480-485
2000 – 2009
- 2009
- [j20]Shih-Hsu Huang, Jheng-Fu Yeh, Chun-Hua Cheng:
An ILP approach to surge current minimization in high-level synthesis. IEICE Electron. Express 6(14): 979-985 (2009) - [j19]Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan:
Synthesis of Anti-Aging Gated Clock Designs. J. Inf. Sci. Eng. 25(6): 1651-1670 (2009) - [j18]Shih-Hsu Huang, Chun-Hua Cheng, Da-Chen Tzeng:
Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization. J. Inf. Sci. Eng. 25(6): 1707-1722 (2009) - [j17]Shih-Hsu Huang, Chun-Hua Cheng:
Minimum-Period Register Binding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1265-1269 (2009) - [j16]Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh:
Opposite-phase register switching for peak current minimization. ACM Trans. Design Autom. Electr. Syst. 14(1): 14:1-14:29 (2009) - [c27]Shih-Hsu Huang, Chun-Hua Cheng:
Timing driven power gating in high-level synthesis. ASP-DAC 2009: 173-178 - [c26]Jheng-Fu Yeh, Chun-Hua Cheng, Shih-Hsu Huang:
Surge Current Minimization in High-level Synthesis. ISCAS 2009: 1513-1516 - 2008
- [j15]Chun-Hua Cheng, Shih-Hsu Huang, Wen-Pin Tu:
Module binding for low power clock gating. IEICE Electron. Express 5(18): 762-768 (2008) - [j14]Shih-Hsu Huang, Chun-Hua Cheng:
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(1): 375-382 (2008) - [j13]Shih-Hsu Huang, Chun-Hua Cheng:
Power-Management Scheduling for Peak Power Minimization. J. Inf. Sci. Eng. 24(6): 1647-1668 (2008) - [c25]Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu:
Type-matching clock tree for zero skew clock gating. DAC 2008: 714-719 - 2007
- [j12]Shih-Hsu Huang, Chun-Hua Cheng:
Operation scheduling for the synthesis of false loop free circuits. IEICE Electron. Express 4(14): 448-454 (2007) - [j11]Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu:
Opposite-Phase Clock Tree for Peak Current Reduction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2727-2735 (2007) - [j10]Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh:
A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains. J. Inf. Sci. Eng. 23(6): 1681-1705 (2007) - [j9]Shih-Hsu Huang, Yow-Tyng Nieh:
Clock skew scheduling with race conditions considered. ACM Trans. Design Autom. Electr. Syst. 12(4): 45 (2007) - [c24]Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh:
Clock Period Minimization with Minimum Delay Insertion. DAC 2007: 970-975 - [c23]Shih-Hsu Huang, Chu-Liao Wang, Man-Lin Huang:
A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs. EUC 2007: 507-516 - [c22]Wei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng:
Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. EUC Workshops 2007: 638-647 - 2006
- [j8]Shih-Hsu Huang, Chun-Hua Cheng:
An ILP Approach to the Slack Driven Scheduling Problem. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(6): 1852-1858 (2006) - [j7]Shih-Hsu Huang, Yow-Tyng Nieh:
Synthesis of nonzero clock skew circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 961-976 (2006) - [c21]Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang:
Peak Power Minimization through Power Management Scheduling. APCCAS 2006: 868-871 - [c20]Shih-Hsu Huang, Chun-Hua Cheng:
Operation Scheduling for False Loop Free Circuits. APCCAS 2006: 1619-1622 - [c19]Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh:
Fast multi-domain clock skew scheduling for peak current reduction. ASP-DAC 2006: 254-259 - [c18]Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu:
Register binding for clock period minimization. DAC 2006: 439-444 - [c17]Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh:
State re-encoding for peak current minimization. ICCAD 2006: 33-38 - [c16]Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang:
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. JCIS 2006 - [c15]Shih-Hsu Huang, Shi-Zhi Liu, Yi-Rung Chen, Jian-Yuan Lai:
High-Speed Fuzzy Inference Processor Using Active Rules Identification. JCIS 2006 - 2005
- [j6]Shih-Hsu Huang, Chung-Hsin Chiang, Chun-Hua Cheng:
Three-dimension scheduling under multi-cycle interconnect communications. IEICE Electron. Express 2(4): 108-114 (2005) - [j5]Shih-Hsu Huang, Jian-Yuan Lai:
A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities. IEICE Trans. Inf. Syst. 88-D(10): 2410-2416 (2005) - [j4]Shih-Hsu Huang, Jian-Yuan Lai:
High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions. J. Inf. Sci. Eng. 21(3): 607-626 (2005) - [c14]Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu:
Minimizing peak current via opposite-phase clock tree. DAC 2005: 182-185 - [c13]Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu:
Race-condition-aware clock skew scheduling. DAC 2005: 475-478 - [c12]Shih-Hsu Huang, Yi-Rung Chen:
VLSI implementation of type-2 fuzzy inference processor. ISCAS (4) 2005: 3307-3310 - [c11]Shih-Hsu Huang, Chun-Hua Cheng:
A formal approach to the slack driven scheduling problem in high-level synthesis. ISCAS (6) 2005: 5633-5636 - [c10]Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh:
Floorplanning with clock tree estimation. ISCAS (6) 2005: 6244-6247 - 2004
- [j3]Shih-Hsu Huang, Yi-Siang Hsu, Chiu-Cheng Lin:
A Timing Driven Crosstalk Optimizer for Gridded Channel Routing. IEICE Trans. Inf. Syst. 87-D(6): 1575-1581 (2004) - 2003
- [c9]Shih-Hsu Huang, Yow-Tyng Nieh:
Clock Period Minimization of Non-Zero Clock Skew Circuits. ICCAD 2003: 809-812 - 2002
- [c8]Shih-Hsu Huang, Wen-Hon Peng, Jian-Yuan Lai:
Automatic synthesis of fuzzy systems based on trapezoid-shaped membership functions. APCCAS (2) 2002: 43-46 - [c7]Shih-Hsu Huang, Yi-Siang Hsu:
A timing driven approach for crosstalk minimization in gridded channel routing. APCCAS (1) 2002: 263-266 - [c6]Shih-Hsu Huang, Chu-Liao Wang:
An effective floorplan-based power distribution network design methodology under reliability constraints. ISCAS (1) 2002: 353-356 - 2001
- [c5]Shih-Hsu Huang, Jian-Yuan Lai:
A High Speed VLSI Fuzzy Logic Controller With Pipeline Architecture. FUZZ-IEEE 2001: 1054-1057 - [c4]Shih-Hsu Huang:
An effective low power design methodology based on interconnect prediction. SLIP 2001: 189-194 - 2000
- [c3]Mely Chen Chi, Shih-Hsu Huang:
A Reliable Clock Tree Design Methodology for ASIC Designs. ISQED 2000: 269-274
1990 – 1999
- 1995
- [j2]Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang:
A new approach to schedule operations across nested-ifs and nested-loops. Microprocess. Microprogramming 41(1): 37-52 (1995) - [j1]Shih-Hsu Huang, Yu-Chin Hsu, Yen-Jen Oyang:
A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits. Microprocess. Microprogramming 41(7): 501-519 (1995) - [c2]Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang:
Synthesis of false loop free circuits. ASP-DAC 1995 - 1992
- [c1]Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang:
A new approach to schedule operations across nested-ifs and nested-loops. MICRO 1992: 268-271
Coauthor Index
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