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2020 – today

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2023
[j4]
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Sheng-Jung Yu, Yu-Chi Lee, Liang-Hsin Lin, Chia-Hsiang Yang:
An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices. IEEE J. Solid State Circuits 58(6): 1810-1819 (2023)
[j3]
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Shaokai Lin, Yatin A. Manerkar, Marten Lohstroh, Elizabeth Polgreen, Sheng-Jung Yu, Chadlia Jerad, Edward A. Lee, Sanjit A. Seshia:
Towards Building Verifiable CPS using Lingua Franca. ACM Trans. Embed. Comput. Syst. 22(5s): 155:1-155:24 (2023)
[c7]
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  - conf/cpsweek/YuIPCVFMS0S23
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Sheng-Jung Yu, Inigo Incer, Valmik Prabhu, Anwesha Chattoraj, Eric Vin, Daniel J. Fremont, Ankur Mehta, Alberto L. Sangiovanni-Vincentelli, Shankar Sastry, Sanjit A. Seshia:
Symbiotic CPS Design-Space Exploration through Iterated Optimization. CPS-IoT Week Workshops 2023: 92-99
[c6]
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Sheng-Jung Yu, Inigo Incer, Alberto L. Sangiovanni-Vincentelli:
Contract Replaceability for Ensuring Independent Design using Assume-Guarantee Contracts. MEMOCODE 2023: 111-121
[c5]
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Sheng-Jung Yu, Inigo Incer, Alberto L. Sangiovanni-Vincentelli:
Constraint-Behavior Contracts: A Formalism for Specifying Physical Systems. MEMOCODE 2023: 180-190
[i1]
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  - journals/corr/abs-2303-17751
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Inigo Incer, Apurva Badithela, Josefine Graebener, Piergiuseppe Mallozzi, Ayush Pandey, Sheng-Jung Yu, Albert Benveniste, Benoît Caillaud, Richard M. Murray, Alberto L. Sangiovanni-Vincentelli, Sanjit A. Seshia:
Pacti: Scaling Assume-Guarantee Reasoning for System Analysis and Design. CoRR abs/2303.17751 (2023)
2022
[j2]
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  - journals/tcad/LuCYC22
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Yu-Sheng Lu, Yan-Lin Chen, Sheng-Jung Yu, Yao-Wen Chang:
Topological Structure and Physical Layout Co-Design for Wavelength-Routed Optical Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2237-2249 (2022)
[j1]
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Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang:
On-Chip Optical Routing With Provably Good Algorithms for Path Clustering and Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4653-4666 (2022)
2021
[c4]
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  - conf/asscc/YuLY21
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Sheng-Jung Yu, Yu-Chi Lee, Chia-Hsiang Yang:
A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices. A-SSCC 2021: 1-3
2020
[c3]
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  - conf/aspdac/YuKHJ20
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Sheng-Jung Yu, Chen-Chien Kao, Chia-Han Huang, Iris Hui-Ru Jiang:
Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability. ASP-DAC 2020: 133-138
[c2]
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  - conf/dac/LuYC20
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Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang:
Topological Structure and Physical Layout Codesign for Wavelength-Routed Optical Networks-on-Chip. DAC 2020: 1-6
[c1]
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Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang:
A Provably Good Wavelength-Division-Multiplexing-Aware Clustering Algorithm for On-Chip Optical Routing. DAC 2020: 1-6

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