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2020 – today

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2023
[c6]
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  - conf/aspdac/YehCCTFKC23
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Yeu-Haw Yeh, Simon Yi-Hung Chen, Hung-Ming Chen, Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, Po-Yang Chen:
DPRoute: Deep Learning Framework for Package Routing. ASP-DAC 2023: 277-282
2022
[c5]
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Hao-Yu Chi, Simon Yi-Hung Chen, Hung-Ming Chen, Chien-Nan Liu, Yun-Chih Kuo, Ya-Hsin Chang, Kuan-Hsien Ho:
Practical Substrate Design Considering Symmetrical and Shielding Routes. DATE 2022: 951-956
[c4]
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Yeu-Haw Yeh, Simon Yi-Hung Chen, Hung-Ming Chen, Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, Po-Yang Chen:
Substrate Signal Routing Solution Exploration for High-Density Packages with Machine Learning. VLSI-DAT 2022: 1-4
2020
[j1]
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Jianli Chen, Zhifeng Lin, Yun-Chih Kuo, Chau-Chin Huang, Yao-Wen Chang, Shih-Chun Chen, Chun-Han Chiang, Sy-Yen Kuo:
Clock-Aware Placement for Large-Scale Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5042-5055 (2020)
[c3]
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Jyun-Ru Jiang, Yun-Chih Kuo, Simon Yi-Hung Chen, Hung-Ming Chen:
On Pre-Assignment Route Prototyping for Irregular Bumps on BGA Packages. DATE 2020: 1311-1314

2010 – 2019

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2017
[c2]
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Yun-Chih Kuo, Chau-Chin Huang, Shih-Chun Chen, Chun-Han Chiang, Yao-Wen Chang, Sy-Yen Kuo:
Clock-aware placement for large-scale heterogeneous FPGAs. ICCAD 2017: 519-526
2016
[c1]
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Chau-Chin Huang, Yen-Chun Liu, Yu-Sheng Lu, Yun-Chih Kuo, Yao-Wen Chang, Sy-Yen Kuo:
Timing-driven cell placement optimization for early slack histogram compression. DAC 2016: 81:1-81:6

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