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ORCIDISPD 2022: Virtual Event, Canada
- Laleh Behjat, Stephen Yang:
ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27 - 30, 2022. ACM 2022, ISBN 978-1-4503-9210-5
Session 1: Opening Session and First Keynote
- Dean Drako:
The Need for Speed: From Electric Supercars to Cloud Bursting for Design. 1
Session 2: Placement, Clock Tree Synthesis, and Optimization
- Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang:
RTL-MP: Toward Practical, Human-Quality Chip Planning and Macro Placement. 3-11 - Chien-Pang Lu, Iris Hui-Ru Jiang, Chih-Wen Yang:
Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines. 13-20 - Sarp Özdemir, Mohammad Khasawneh, Smriti Rao, Patrick H. Madden:
Kernel Mapping Techniques for Deep Learning Neural Network Accelerators. 21-28
Session 3: Design Flow Advances with Machine Learning and Lagrangian Relaxation
- Matthew M. Ziegler, Lakshmi N. Reddy, Robert L. Franch:
Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning. 29-37 - David G. Chinnery
, Ankur Sharma:
Integrating LR Gate Sizing in an Industrial Place-and-Route Flow. 39-48 - Vishal Khandelwal:
Machine-Learning Enabled PPA Closure for Next-Generation Designs. 49 - Narender Hanchate:
Improving Chip Design Performance and Productivity Using Machine Learning. 51
Session 4: Panel on Traditional Algorithms Versus Machine Learning Approaches
- Patrick R. Groeneveld:
From Hard-Coded Heuristics to ML-Driven Optimization: New Frontiers for EDA. 53 - Haoxing Ren:
Embracing Machine Learning in EDA. 55-56 - Mohammad T. Khasawneh, Patrick H. Madden:
What's So Hard About (Mixed-Size) Placement? 57-64 - Summer Yue, Ebrahim M. Songhori, Joe Wenjie Jiang, Toby Boyd, Anna Goldie, Azalia Mirhoseini, Sergio Guadarrama:
Scalability and Generalization of Circuit Training for Chip Floorplanning. 65-70
Session 5: Second Keynote
- Jean-Philippe Fricker:
The Cerebras CS-2: Designing an AI Accelerator around the World's Largest 2.6 Trillion Transistor Chip. 71
Session 6: Third Keynote
- Andrew B. Kahng:
Leveling Up: A Trajectory of OpenROAD, TILOS and Beyond. 73-79
Session 7: Prototyping, Packaging, and Integration
- Ming Zhang:
3DIC Design: Challenges and Opportunities in System-of-Chips Integration. 81 - Armen Kteyan, Jun-Ho Choy, Valeriy Sukharev, Massimo Bertoletti, Carmelo Maiorca, Rossana Zadra, Massimo Inzaghi, Gabriele Gattere, Giancarlo Zinco, Paolo Valente, Roberto Bardelli, Alessandro Valerio, Pierluigi Rolandi, Mattia Monetti, Valentina Cuomo, Salvatore Santapa:
Novel Methodology for Assessing Chip-Package Interaction Effects onChip Performance. 83-89 - Alex Rabinovitch:
On Ensuring Congruency with Implementation During Emulation and Prototyping. 91
Session 8: 3D IC Design
- Sandeep Kumar Goel:
Challenges and Solutions for 3D Fabric: A Foundry Perspective. 93 - Tanay Karnik:
Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration. 95 - Gauthaman Murali, Sandra Maria Shaji, Anthony Agnesina, Guojie Luo, Sung Kyu Lim:
ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs. 97-104 - Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Charlie Chung-Ping Chen:
Intelligent Design Automation for Heterogeneous Integration. 105-106
Session 9: Routing
- Po-Yan Chen, Bing-Ting Ke, Tai-Cheng Lee, I-Ching Tsai, Tai-Wei Kung, Li-Yi Lin, En-Cheng Liu, Yun-Chih Chang, Yih-Lang Li, Mango C.-T. Chao:
A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction. 107-115 - Diwesh Pandey, Gustavo E. Téllez, James Leland:
LEO: Line End Optimizer for Sub-7nm Technology Nodes. 117-125 - Sai Pentapati, Sung Kyu Lim:
Routing Layer Sharing: A New Opportunity for Routing Optimization in Monolithic 3D ICs. 127-134
Session 10: Fourth Keynote
- Aiqun Cao:
Triple-play of Hyperconvergency, Analytics, and AI Innovations in the SysMoore Era. 135
Session 11: Lifetime Achievement Commemoration for Ricardo Reis
- Ricardo Augusto da Luz Reis:
A Lifetime of Physical Design Automation and EDA Education: ISPD 2022 Lifetime Achievement Award Bio. 137-138 - Giovanni De Micheli:
Design and Optimization of Quantum Electronic Circuits. 139 - Renato Hentschke:
Physical Design at the Transistor Level Beyond Standard-Cell Methodology. 141-143 - Ricardo Augusto da Luz Reis:
Physical Design Optimization, From Past to Future. 145-148
Session 12: Fifth Keynote
- Sameer Halepete:
Accelerating the Design and Performance of Next Generation Computing Systems with GPUs. 149-150
Session 13: Advances in Analog and Full Custom Design Automation
- Jürgen Scheible:
Optimized is Not Always Optimal - The Dilemma of Analog Design Automation. 151-158 - Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar:
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. 159-166 - Helmut Graeb:
Analog Synthesis - The Deterministic Way. 167-174 - Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, Haoxing Ren:
AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies. 175-183
Session 14: Panel on Challenges and Approaches in VLSI Routing
- Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan:
Challenges and Approaches in VLSI Routing. 185-192 - Wen-Hao Liu, Bing Chen, Hua-Yu Chang, Gary Lin, Zi-Shen Lin:
Challenges for Automating Package Routing. 193-194
Session 15: Global Placement, Macro Placement, and Legalization
- Xiang Gao, Yi-Min Jiang, Lixin Shao, Pedja Raspopovic, Menno E. Verbeek, Manish Sharma, Vineet Rashingkar, Amit Jalota:
Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble. 195-202 - Donghao Fang, Boyang Zhang, Hailiang Hu, Wuxi Li, Bo Yuan, Jiang Hu:
Global Placement Exploiting Soft 2D Regularity. 203-210 - Chung-Hsien Wu, Wai-Kei Mak, Chris Chu:
Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement. 211-218
Session 16: Sixth Keynote
- Ingrid Verbauwhede:
Hardware Security: Physical Design versus Side-Channel and Fault Attacks. 219-220
Session 17: ISPD 2022 Contest Results and Closing Remarks
- Johann Knechtel, Jayanth Gopinath, Mohammed Ashraf, Jitendra Bhandari, Ozgur Sinanoglu, Ramesh Karri:
Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest. 221-228
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