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ORCID15th ASICON 2023: Nanjing, China
- 15th IEEE International Conference on ASIC, ASICON 2023, Nanjing, China, October 24-27, 2023. IEEE 2023, ISBN 979-8-3503-1298-0
- Zhong Zhao, Ping Luo, Zhiyuan Zhang, Jiahang Fan, Hao Chen, Bo Zhang:
A low ripple Frequency-Feedback PFM-PWM Buck converter with seamless mode transition. 1-4 - Rixian Tang, Lixia Zheng, Ruiming Zhong, Jin Wu:
A 64×64 active and passive imaging readout circuit based on HgCdTe-LMAPD. 1-4 - Jing Li, Tianci Zhang, Yingchen Liu, Penghao Jiang, Zhong Zhang, Qihui Zhang, Ning Ning, Qi Yu:
A 59.99dB SNDR 1.13mW Ping-pong NS SAR ADC for 3-D Transesophageal Echocardiography. 1-4 - Wenli Liao, Chengying Chen, Daifa Gao, Yufei Huang:
A 10Gbps High-Speed Low-Noise Optical Receiver Based on CMOS 45nm Technology. 1-4 - Yichen Ouyang, Xianglong Wang, Gang Shi, Lei Chen, Fengwei An:
A Dynamic Codec with Adaptive Quantization for Convolution Neural Network. 1-4 - Shengyuan Zhou, Ziyao Xia, Chao Yang, Xiaoming Liu, Sheng Wang, Jing Jin:
Fast locking Sampling PLL Using Phase Error Eliminator. 1-4 - Bisheng Chen, Xiayu Li, Jicheng Lu, Jun Yu:
A Reusable AI acceleration Architecture based on Matrix Multiplication for Convolutional Neural Network with Digital Signal ProcessingTasks. 1-4 - Xuehang Yang, Wei Li, Shushi Chen, Leilei Huang, Yibo Fan:
A Dynamic-Texture-Guided Fast Algorithm for Geometric Partitioning Mode of VVC. 1-4 - Jide Zhang, Kaixiang Zhu, Kaichuang Shi, Lingli Wang, Hao Zhou:
Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes. 1-4 - Sujuan Liu, Shibo Li, Xudong Sun:
A Low-Complexity Timing Skew Mismatch Calibration Method for Time-Interleaved ADCs. 1-4 - Kaifan Jiang, Jun Yu:
A Digital Clock and Data Recovery Architecture with Precise Voting for Multi-Gigabit/s Links. 1-4 - Wenyu Huang, Yifan Shi, Wenyue Zhou, Jiaqian Ling, Xiaohu You, Chuan Zhang:
Low-Complexity GAI-BP Detection for MIMO Systems with Threshold-Updating Strategy. 1-4 - Chongzheng Fang, Chenhui Zhou, Fan Ye:
A Common Architecture for Digital Process of Ultrasonic Imaging System after AFE. 1-4 - Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi
, Makoto Nakamura:
High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS. 1-2 - Zhen Yan, Minoru Fujishima, Satoshi Tanaka, Takeshi Yoshida:
Suppression of Reflections and Elimination of Transmission Disparities in Differential Crossover Line Junctions. 1-4 - Moufu Kong, Zeyu Cheng, Ning Yu, Rui Jin, Jiaxin Guo, Hongqiang Yang:
An Ultra-low Specific On-resistance SiC LDMOS Using Double RESURF and Field Plate Techniques. 1-4 - Kejia Zhu:
A Novel Programmable Risistance and Capacitance Network for High-Precision Analog Design. 1-4 - Songlei Meng, Ziyang Deng, Yun Wang, Hongtao Xu:
A 293-to-303 GHz Fundamental VCO with -4dBm Peak Output Power in 40nm CMOS. 1-4 - Zehua Chen, Ziyuan Chu, Taijia Zhang, Xinyi Li, Yuyin Sun, Yimeng Zhang, Yuming Zhang:
A 0.69% LED Current Error LED Driver with Hysteretic Current Control. 1-4 - PuSen Wu, Liji Wu, Hao Xue, Zhenhui Zhang, Byambajav Ragchaa, Xiangmin Zhang:
A High-precision Current Detection Circuit for Battery Management System. 1-4 - Hu Ge, Qiao Yuan, Yuhao Zhang, Yukun Song, Zhenmin Li:
Design of a Data Transmission Control Unit in a Multi-core DSP System. 1-4 - Xianhe Liu, Qiang Wu, Yanli Li, Qi Wang:
Improved BEOL Design Rules With 45-Degree Local Interconnection. 1-4 - Chenyang Li, Chunsheng Jiang, Hongying Chen:
Investigation of electrical characteristics of a novel FeFET-based relaxation oscillator. 1-3 - Duo Sheng, Ying-Chi Chiu, Yun-Quan Li, You-Ning Lo, Chao-Kai Pai, Ten-Ling Wang:
A Digital Receive Beamforming IC for High-Frequency Ultrasound Imaging System. 1-4 - Sujuan Liu, Jiajun Ma, Yichen Liang:
FPGA Implementation of High Critical Sparsity Orthogonal Matching Pursuit Algorithm for Compressed Sensing Reconstruction. 1-4 - Wuxin Ge, Chao Wang:
Efficient Layout Pattern Matching Based on Local Information. 1-4 - Yufan Chen, Xuyang Duan, Jun Han:
UACT: A Unified Energy-efficient Computing Architecture for CNN and TCNN. 1-4 - Qi Chen, Dayou Zhang, Jiawei Fu, Yuhui He:
Optimizing Supervised Learning of Deep Spiking Neural Network towards Memristor Crossbar Implementation. 1-4 - Leiou Wang, Donghui Wang:
A Model-Guided Underwater Image Enhancement Network. 1-4 - Hiroshi Iwai:
Development of RFCMOS Technologies in the 1990s in Toshiba. 1-18 - Kexin Wang, Jundong Xie, Yiwei Wang, Chang Wu:
An Efficient Scheduling Algorithm for Stream Computing. 1-4 - José Gabriel F. Coutinho, Ce Guo, Tim Todman, Wayne Luk:
Exploring Machine Learning Adoption in Customisable Processor Design. 1-4 - Haruo Kobayashi:
Signal Generation Technologies for Analog/Mixed-Signal IC Testing. 1-4 - Yuchao Zhang, Zihao Xuan, Yi Kang:
A 28nm 15.09nJ/inference Neuromorphic Processor with SRAM-Based Charge Domain in-Memory-Computing. 1-4 - Shengnan Zhou, Xiangyu Mao, Cheng Huang, Rui Paulo Martins, Yan Lu:
A 23-nA Quiescent Current Output-Capacitorless LDO Regulator for IoT Devices. 1-4 - Wenjun Li, Bingjie Chen, Jianhua Feng:
An Improved Frequency Compensation Scheme for a Low Quiescent Current Low Dropout Voltage Regulator with Wide Input Voltage and Load Current Range. 1-4 - Jyh-Chyurn Guo, Chih-Shiang Chang:
The Impact of Strain and Layout Dependent Effects on High Frequency Performance and Low Frequency Noise in Nanoscale Devices. 1-4 - Yudi Qiu, Shiyan Yi, Ming-e Jing, Xiankui Xiong, Dong Xu, Xuanpeng Zhu, Xiaoyang Zeng, Yibo Fan:
Performance Error Evaluation of gem5 Simulator for ARM Server. 1-4 - Ruiyang Ji, Wenyue Zhou, Xiaosi Tan, Xiaohu You, Chuan Zhang:
Improved GAI-BP Detection for MIMO Systems Based on Message Post-Processing. 1-4 - Mengxuan Wang, Yuan Linghu, Chang Wu:
A General-Purpose Compiler Design for Instruction-Based AI Accelerator Implementation. 1-4 - Yeping Zheng, Tingting Li, Wei Li, Faxing Lei, Jiarui Liu, Yibo Fan:
A Low-Complexity Algorithm for JPEG-LS-Based RAW Domain Compression. 1-4 - Zihao Ye, Xuecong Lu, Shuai Wang, Bing Li:
An 842 nW Wearable Inter-Patient Cardiac Arrhythmia Monitoring Processor with a Feature Engine-Based Artificial Neural Network. 1-4 - Hongli Tian, Xiaodi Xing, Jian Zhang, Shaodi Wang, Yuan Wang:
Design and Implementation of a Special Operator for Neural Networks Based on Noise Reduction and Super Resolution. 1-4 - Yaxin Zeng, Hao Xu, Xi Feng, Na Yan:
Analysis and Modeling of Non-ideal Effects in SAR ADC. 1-4 - Hongshuai Wei, Yuejun Zhang, Huihong Zhang, Yang Wang, Tengfei Yuan, Chengjie Wang, Pengjun Wang:
An Efficient Hash Computing Unit for Kyber Algorithm. 1-4 - Po-Heng Pao, Ren-Hao Cheng, Yi-Hsiu Huang, Yu-Ying Yang, Tzu-Hsien Sang, Chia-Ming Tsai, Chao-Hsin Chien:
Noncontact Remote Doping for High-performance Two-dimensional Electronics. 1-4 - Weirong Xi, Jianhua Jiang, Chengying Chen:
A Fully-integrated Analog Front-end for Carbon-based Short-wave Infrared Image Sensor. 1-4 - Wen Zuo, Wei Li, Yun Wang, Yue Lin, Hongtao Xu:
A 115-325MHz Wideband Analog Baseband with 0.5dB-Step Variable Gain Amplifier and Six-order Reconfigurable Gm-C Lowpass Filter. 1-4 - Jae-Hyoun Park:
Multi-channel 600V-level Driver for Piezoelectric-Electrohydrodynamic Hybrid Inkjet Printer. 1-4 - Shuaichen Mu, Xiaoyu Guo, Hongge Li:
A 256-channel 11-bit OLED Source Driver IC with Unit Current Calibration. 1-4 - Yanli Li, Xianhe Liu, Qi Wang, Qiang Wu:
A Further Analysis of the Forbidden Pitch in Photolithography in Advanced Technology Nodes. 1-4 - Zhaolin Yang, Jing Jin, Yuyang Chen, Jianjun Zhou, Xiaoming Liu:
A Wideband Inductorless LNA Employing Dual-Loop Feedback for Low-Power Applications. 1-4 - Heng Zhang, Yuan Du, Li Du:
Linearity Analysis for Charge Domain In-memory Computing. 1-4 - Yonghui Wu, Yiwei Liu, Shaowei Zhen, Yanliang Li, Yikang Li, Jia-Ning Zhang, Yi Ou, Bo Zhang:
A High Precision Capacitive Isolation Amplifier for Current Sensing Applications. 1-3 - Zekun Zhou, Yun Dai, Jianli Lou, Yue Shi, Bo Zhang:
A High Precision Current Sampling Circuit with Rail-to-Rail Common-Mode Input Range. 1-5 - Jason Chun Lok Li, Rui Lin, Jiajun Zhou, Edmund Yin Mun Lam, Ngai Wong:
A Unifying Tensor View for Lightweight CNNs. 1-4 - Xilong Shao, Xuejiao Ma, Gang Li:
Design of Lightweight Strong Arbiter PUF Circuit Based on MOSFET Threshold Loss. 1-4 - Haizhun Wang, Xiudeng Wang, Yinshui Xia:
Sub-50mV Bootstrap Clock Booster and Integrated Cold Start for Thermoelectric Energy Harvesting. 1-4 - Johar Abdekhoda, Li Wang, Reza Sarvari, Chik Patrick Yue:
A Bang-Bang Phase Detector for PAM-N Signaling. 1-4 - Guang Chen, Binglong Li:
Design and Implementation of High-speed Reconfigurable Multi-core Network Security Protocol Analyse Processor. 1-4 - Yuan Li, Pingqiang Zhou:
Full-Chip Voltage Prediction via Graph Attention Based Neural Networks. 1-4 - Wuqiong Zhao, Changhan Li, Zhenhao Ji, You You, Xiaohu You, Chuan Zhang:
Automatic Timing-Driven Top-Level Hardware Design for Digital Signal Processing. 1-4 - Haonan He, Pengjun Wang, Xiangyu Li, Li Ni, Yuejun Zhang:
Highly Reliable Physical Unclonable Function Based on ZnO-SnO2 Gas Sensor. 1-4 - Anawin Opasatian, Makoto Ikeda:
High-Performance BLS12-381 Pairing Engine on FPGA. 1-4 - Xinyi Tang, Nick Tao, Yang Jiang, Qing Wang, Fangzhou Du, Hongyu Yu:
Recess-Patterned Ohmic Contact Technology for AlGaN/GaN Heterostructures. 1-4 - Wanlong Zhao, Yuejun Zhang, Mingze Ren, Liang Wen, Pengjun Wang:
A 7nm-Based Decodable Self-Resetting Regfile Circuit. 1-4 - Yuxin Li, Zhenxia Duan, Jie Wang, Zijian Zhou, Ming Yang, Enqi Wu, Lin Du:
Glass Wet Deep Etching for Fabricating Biomimetic Devices in Biosensing. 1-4 - Kazutoshi Kobayashi:
Scalable Highly Integrated Quantum Bit Error Correction System by Classical Electronics. 1 - Zhengyi Zhang, Yuanda Yang, Lingli Wang:
Rabbit: An Efficient Verification Platform Base on Virtual Peripherals. 1-4 - Zhiyuan Cao, Chengcheng Zhang, Zirui Jin, Dongsheng Liu:
A DC Offset Cancellation Circuit Using Digital Assistance Technique and Self-Calibrating Comparator for RF Transceiver. 1-4 - Junhui Ye, Dongyin Mao, Wentao Zheng:
Design of a Low Temperature Drift High Power Supply Rejection Bandgap Reference Circuit. 1-4 - Xilin Lai, Lei Xu, Shuo Liu, Junling Liu, Ming He:
Bi2O2Se/P3HT Heterotransistors for Broadband Photodetections with High Rhotoresponsivities of 106 A/W. 1-3 - Beicheng Xue, Zhifei Lu, Wei Zhang, He Tang, Xizhu Peng:
A Sinusoidal Fitting-based Digital Foreground Calibration Technique for Pipelined ADC. 1-4 - Guoqiang Song, Wenxin Yan, Junhui Zhang, Lin He:
A Transient-Enhanced Digital-LDO With Adaptive Clock-Edge Control. 1-4 - Haruo Kobayashi, Manato Hirai, Kakeru Otomo, Shogo Katayama, Xueyan Bai, Masashi Chiba, Zifei Xu, Dan Yao, Lengkhang Nengvang, Minh Tri Tran, Kanji Yoshihiro, Anna Kuwana, Takato Ooide, Hiroshi Tanimoto, Yuji Gendai, Jianglin Wei:
Back to the Analog Neural Network and Linear Circuit Theory. 1-4 - Zhenhao Ji, Ruiyang Ji, Mingyuan Ding, Xiangning Song, Xiaohu You, Chuan Zhang:
Hardware Implementation of Chromatic Dispersion Compensation in Finite Fields. 1-4 - Zekai He, Wei Li, Leilei Huang, Yibo Fan:
A High-Throughput Luma Mapping with Chroma Scaling Decoder for Versatile Video Coding. 1-4 - Feng Dan Lin, Kang Leo Zhao:
Receiver Characterization with On-Die Eye Monitor (ODEM) in LPDDR5 and DDR5 SDRAM. 1-4 - Yajie Zhao, Yizhou Jiang, Weiming Hu, Yajie Qin:
A High Linearity Large Time Constants Switched-Resistor Filter for Biomedical Applications. 1-4 - Jiuhe Wang, Jian Liu, Yong Xu, Yulong Jiang, Jing Wan:
An Active Pixel Sensor Array based on Compact Photoelectron In-situ Sensing Device (PISD). 1-3 - Xiangjian Kong, Ding Qiu, Mingchao Jian, Chunbing Guo, Kai Xu:
A Dual-Core Quad_Mode VCO with Reconfigurable Magnetic Coupling Mode and Negative-Resistive Mode Switch. 1-4 - Junting Chen, Chengcai Wang, Zuoheng Jiang, Mengyuan Hua:
Processes of p-GaN Gate HEMTs for High-efficiency and High-reliability Applications. 1-4 - Yefan Liu, Yunfeng Wu, Liang Chen, Polaron Cao, Yuliang Zhou, Vincent Zhang:
Overcoming the challenges of ReRAM towards mass production from the perspectives of process, design and application. 1-4 - Bokai Zeng, Chen Yang, Hui Zhao, Xiang Qiu:
A Performance-driven Neural Network Compiler for Multi-core Computing-In-Memory Accelerator. 1-4 - Minwei Hu, Jin Wu, Chenggong Wan, Lixia Zheng:
A Region of Interest Technique for Event Driven Typed SPAD Readout Circuit. 1-4 - Jianwen Lin, Linlin Cai, Yutao Chen, Haoyu Zhang, Wangyong Chen:
Machine Learning-Assisted Single-Event Transient Model of 12nm FinFETs for Circuit-Level Simulation. 1-4 - Xiangyu Dai, Jinghui Li, Zhengfang Qian:
Study on the Performance of Flexible Curved Inverted-F Antenna under Compound Deformation Condition. 1-4 - Hang Xu, Chenjia Xie, Xin Lu, Li Du, Yuan Du:
Memory-Efficient Compression Based on Least-Squares Fitting in Convolutional Neural Network Accelerators. 1-4 - Weizhen Cai, Jianjun Zhou, Xiaobo Chen, Xiaoming Liu:
A High Precision CMOS Temperature Detector with Curvature Calibration Technique. 1-4 - Hangbiao Li, Ran Zhang, Kai Zhang, Xiaodong Zhao, Zhiqing Liu, Shuai Liu:
A Driver Amplifier with Configurable Transformer-Based Matching Networks in 65-nm CMOS. 1-4 - Siyuan Li, Yong Xu, Jing Wan:
Comparisons of Photodiodes Based on Bulk-Silicon and Silicon-on-Insulator Substrates. 1-3 - Zheng Chai, Weidong Zhang, Jian Fu Zhang:
Stochastic Computing Based on Volatile Ovonic Threshold Switching Devices. 1-4 - Xing Zhou, Siau Ben Chiah:
Scalable Compact Model for High-frequency GaN-HEMTs. 1-4 - Yunhao Li, Wei Li, Yun Wang, Wei Luo, Yue Lin, Hongtao Xu:
A Compact 144% Fractional Bandwidth CMOS Power Amplifier With an Optimization of Synthesized High-Order Matching Network. 1-4 - Hao Chen, Shenhao Jiang, Shaowei Zhen, Yajuan He, Hailiang Xiong, Xin Chen, Hongyang Wu, Liang Huang, Yongsheng Du, Bo Zhang:
A Fast-Transient Right-Half-Plane Zero-Free Hybrid Buck-Boost Converter. 1-3 - Moufu Kong, Ke Huang, Ronghe Yan, Bo Yi, Bingke Zhang, Hongqiang Yang:
A Novel SiC Superjunction Trench MOSFET with Integrated Heterojunction Diode for Improved Performance. 1-4 - Jiaxu Zhou, Jing Jin, Yichao Lin, Shan Wang, Bo Wang, Tingting Mo:
A 24/48 Gb/s NRZ/PAM-4 Dual-Mode Transmitter with 3-tap FFE in 28 nm CMOS. 1-4 - Moufu Kong, Zhi Lin, Hongfei Deng, Bo Yi, Rui Jin, Hongqiang Yang:
A Novel 1200-V Class SiC MOSFET With Schottky Barrier Diode for Improved third quadrant performance. 1-4 - Weixiong Qiu, Shihui Sun, Yufei Ai, Wengao Lu, Yacong Zhang, Zhongjian Chen:
A 128-electrodes Neural Probe with 30*55 µm2 Channel Area Low-power CCO-based ADC. 1-4 - Mingyue Zheng, Wangyong Chen, Yaoyang Lyu, Haifeng Chen, Jiahui Chen, Linlin Cai:
Enhancing Temperature Immunity of Digital Circuit Against Aging : The Standard Cell Subset Method. 1-4 - Sicheng Han, Xueyin Wu, Wei Li, Yun Wang, Yue Lin, Hongtao Xu:
A 4.7-to-18-GHz Ultra-Wideband Variable-Gain Balun-LNA Using 3rd-Order-Band-Pass Input Matching in 40-nm CMOS. 1-4 - Daisuke Kikuta, Ryo Kishida, Kazutoshi Kobayashi:
Ring Oscillators with identical Circuit Structure to Measure Bias Temperature Instability. 1-4 - Jing Yuan, Wenzhong Bao, Tianxiang Wu, Shunli Ma:
High Performance Bootstrap Switch for 14 bit SAR ADC with Redundancy in SMIC 180nm. 1-4 - Jing Mai, Jiarui Wang, Zhixiong Di, Guojie Luo, Yun Liang, Yibo Lin:
OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit. 1-4 - Wei Liu, Xuecong Lu, Yuxi Mao, Bing Li:
A 23.5 μA Ultra-Low Standby Power Microphone ASIC with the Voice Activity Detection Based on A Level-Crossing ADC. 1-4 - Baohui Xu, Rongmei Chen, Jie Liang:
A Modeling Study: Applying Carbon-Based Interconnects to BS-PDN Architecture. 1-4 - Muxi Zou, Shunli Ma, Xiaodi Feng, Junyan Ren, Tianxiang Wu:
A 300MS/s 57.6dB SNDR Single-Channel SAR ADC with Accelerated SAR Logic. 1-4 - Chenggong Wan, Lixia Zheng, Jin Wu:
A SPAD Relative Address Coding for Lateral Resolution Improvement in Coincidence Detection. 1-4 - Jyi-Tsong Lin, Kuan-Pin Lin:
A Simple New Line-Tunneling iTFET with Overlapping Between Gate and Source Contact. 1-4 - Wenyong Zhou, Yuan Ren, Jiajun Zhou, Tianshu Hou, Ngai Wong:
A Time- and Energy-Efficient CNN with Dense Connections on Memristor-Based Chips. 1-4 - Chang Liu, Desheng Zhang, Shuohan Yang, Yinyu Wang, Qingyue Zhou, Shuo Zhang, Run Min, Qiaoling Tong:
An Adaptive Current Source IGBT Gate Driver Based on Current and Voltage Slope Feedback to Reduce EMI. 1-4 - Jiacheng Cao, Ziyi Yang, Jie Lu, Jinmei Lai:
A High-Performance YOLOV5 Accelerator for Object Detection with Near Sensor Intelligence. 1-4 - Yimao Cai, Yi Gao, Zongwei Wang, Lin Bao, Ling Liang, Qilin Zheng, Cuimei Wang, Ru Huang:
Device-Architecture Co-optimization for RRAM-based In-memory Computing. 1-4 - Yang Feng, Yueran Qi, Xuepeng Zhan, Jixuan Wu, Jiezhi Chen:
Flash-based Computing-in-memory Architectures with High-accuracy and Robust Reliabilities for General-purpose Applications. 1-4 - Jin Yan, Eryan Gu, Kun Cao, Huilong Zhou, Rong Chen:
Selective Atomic Layer Deposition to Extend Moore's Law and Beyond: Surface Kinetic Tuning for Self-Aligned Growth. 1-4 - Chunyan Zhao, Xilin Lai, Ming He:
Controllable Growth of P3HT Single-Crystal Films for Organic Field-Effect Transistors. 1-3 - Yaoru Qu, Jian Liu, Yong Xu, Yulong Jiang, Jing Wan:
Photoelectron In-situ Sensing Device with embedded photodiode and interface passivation. 1-3 - Haohan Zhang, Song Cheng, Yi Kang:
FlsGraph: A Parallel Architecture for Large-scale Graph Processing. 1-4 - Jun Zeng, Panfeng Wang, Haili Wang, Hailong Yao, Fuchun Sun:
A Compilation Toolchain of Neural Networks for FPGA Backend. 1-4 - Hao Qiu, Xusheng Zhang, Junji Chen, Yi Shi, Makoto Takamiya:
Transmitter IC Enabling Magnetic Field Shaping for High-Efficiency Wireless Charging of Multiple Receivers. 1-4 - Meiling Yang, Shan Cao, Wei Zhang, Yu Li, Zhiyuan Jiang:
Loop-Tiling Based Compiling Optimization for CNN Accelerators. 1-4 - Su Zheng, Bei Yu, Martin D. F. Wong:
OpenILT: An Open Source Inverse Lithography Technique Framework (Invited Paper). 1-4 - Hang Ling, Yifei Bai, Fengyi Mei, Huajun Yao, Yongzhen Chen, Jiangfeng Wu:
Pipelined-SAR ADC Calibration Technique Based on Gain-Bit Weights. 1-4 - Chaoyang Zheng, Zhipeng Chen, Jianhua Lu, Yan Ma, Yumei Huang, Zhiliang Hong:
A 400M-510MHz On-Chip Transformer-Based RF Power Amplifier with 22.5dBm Output Power and 48% PAE. 1-4 - Jing Li, Penghao Jiang, Tianci Zhang, Yingchen Liu, Zhong Zhang, Qihui Zhang, Ning Ning, Qi Yu:
A Programmable High-Voltage Pulse Transmitter Circuit for 3-D Miniature Ultrasound Probes. 1-4 - Yuzi Wang, Xichen Duan, Kai Sun, Peng Huang, Liuyang Zhang, Jie Liang:
A Bandgap Voltage Reference with Low Temperature Coefficient and High PSRR Designed for LDO. 1-4 - Guohui Zhang, Fen Ge, Fang Zhou:
A Deep Q Network Hardware Accelerator Based on Heterogeneous Computing. 1-4 - Zilu Liu, Li Wang, Hamed Fallah, C. Patrick Yue:
Design of Chip-to-PCB Matching Network for Millimeter-Wave On-Chip Transmitter and On-PCB Antenna. 1-4 - Qiang Cheng, ZhaoCong Wang, Yingxiong Song, Jian Chen, Qianwu Zhang, Nan Ye:
Integration Of Micro Surface Mount Components On Printed Circuit Board By micro-Transfer Printing. 1-3 - Yiyun Mao, Haoyuan Gao, Dejian Li, Hao Xu, Na Yan:
An ADPLL Design Model Based on LoRa IoT Application. 1-4 - Ralph Gerard B. Sangalang, You-Wei Shen, Shiva Reddy, Lean Karlo S. Tolentino, Chua-Chin Wang:
Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS. 1-5 - Xinhao Xu, Yongzhen Chen, Jiangfeng Wu:
A low-power daisy-chain controller implemention in BMS based on power mode switching. 1-4 - Xiaodi Feng, Shunli Ma, Muxi Zou, Tianxiang Wu:
A High Gain and Wide Bandwidth Dual-Power CMOS Op-amp for High-Speed ADCs Application. 1-4 - Jianing Gao, Qiming Shao, Fangyu Deng, Qin Wang, Naifeng Jing, Jianfei Jiang:
An NoC-based CNN Accelerator for Edge Computing. 1-4 - Shuaibo Huang, Jiang Sha, Longxing Shi:
An Analytical Model for Domain-Specific Accelerator Deploying Sparse LU Factorization. 1-4 - Jun Chen, Fengyi Mei, Mingzhe Liu, Yongzhen Chen, Jiangfeng Wu:
A 32GS/s 7bit TI-SAR ADC in 28nm for 32Gb/s ADC-Based SerDes Receiver. 1-4 - Yen-Chen Chang, Wei-Heng Tai, Jyi-Tsong Lin:
Steeper Subthreshold Swing Attained in Ge-Source Inductive Tunneling FET via Epitaxial Tunnel Layer for Suppressed Point Tunneling. 1-4 - Leshan Xu, Takeshi Yoshida, Shunsuke Yabuki, Minoru Fujishima, Satoshi Tanaka:
A 27-to-65-GHz CMOS Amplifier with Tunable Frequency Response. 1-4 - Jing Li, Luhan Yang, Dongjian Chen, Zhong Zhang, Qihui Zhang, Ning Ning, Qi Yu:
Ultra-low-power and High-accuracy CMOS Temperature Sensor. 1-4 - Qingzhen Wang, Wenxian Gu, Hengchang Bi, Liangjian Lyu, Deli Qiao, Xing Wu:
A Spike-Sorting-Assisted Compressed Sensing Processor for High-Density Neural Interfaces. 1-4 - Renjie Wei, Kaifeng Wang, Zhixuan Wang, Libo Yang, Fangxing Zhang, Yongqin Wu, Ye Ren, Le Ye, Lining Zhang, Weihai Bu, Ru Huang, Qianqian Huang:
A Novel TFET-MOSFET Hybrid SRAM for Ultra-Low-Power Applications. 1-4 - Haolin Lu, Ye Zhou, Wengao Lu, Yacong Zhang, Zhongjian Chen:
High Frame Rate High Precision ROIC with Pixel-level CCO-Based ADC for Infrared FPAs. 1-4 - Xudong Wu, Gang Li, Pengjun Wang:
Design of PUF Circuit Based on Charge Leakage of Cascade Dynamic Gate. 1-4 - Seokjin Oh, Rina Yoon, Seungmyeong Cho, Kyeong-Sik Min:
Hardware-Specific Optimization for Mapping of Convolutional Neural Networks to Memristor Crossbars. 1 - Weibo Li, Minghao Jiang, Yongzhen Chen, Jiangfeng Wu:
Complexity-Reduced Joint Calibration for Nonlinearity and I/Q Imbalance in Direct-Conversion Transmitters. 1-4 - Zhenyu Wang, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Jae-Sun Seo, Chaitali Chakrabarti, Ümit Y. Ogras, Vidya A. Chhabria, Yu Cao:
Benchmarking Heterogeneous Integration with 2.5D/3D Interconnect Modeling. 1-4 - Yanming Li, Mengyao Liu, Lufang Zhang:
A Novel 16-bit ADC Based on Third-order Σ-∆ Modulator with Zero Optimization. 1-4 - Jiantao Ye, Fen Ge, Fang Zhou:
A Method of Mapping Convolutional Neural Networks on Resource-limited NoC Platform. 1-4 - Xinyi Lin, Hao Xu, Dejian Li, Na Yan:
A High Speed, Low Power and Low Phase Noise Divider for Wideband Application. 1-4 - Xin Lu, Heng Zhang, Leilei Wang, Tao Fang, Chunhui Zhang, Feng Wang, Li Du, Yashe Liu, Xiangfei Chen, Yuan Du:
A Non-Centralized Routing Scheme with Phase-Caching CDR for Nanosecond-Level Optical Switching Systems. 1-4 - Zonghao Zhang, Xi Wang, Keqiang Ma, Siliang Wang, Chenxing Wang, Haoyang Zhou, Haimeng Huang, Junji Cheng, Bo Yi, Hongqiang Yang:
Temperature Dependent Optimization for Specific On-Resistance for 900 V Superjunction MOSFETs: Numerical Calculation and Comparison. 1-4 - Jianing Gao, Lingyi Liu, Qin Wang, Naifeng Jing, Jianfei Jiang:
High-Performance Genomic Analysis Heterogeneous System Using OpenCL. 1-4 - Sixing Xiong, Kenjiro Fukuda, Takao Someya:
Ultra-flexible organic photovoltaics for powering wearable electronics. 1-4 - Xichen Duan, Yuzi Wang, Peng Huang, Kai Sun, Liuyang Zhang, Jie Liang:
An Analog Assisted Dual Loop Hybrid LDO Based on Adaptive Clock. 1-4 - Yuekai Liu, Jinlei Pan, Liang Qi:
A CT DSM with DAC Scaling Technique for Direct Neural Recording Front-End. 1-4 - Jiankun Li, Zepeng Lin, Fan Ye:
Periodic Analysis of Adaptive LMS Filter in TIADC. 1-4 - Jun Huang, Ning Ning, Renxiong Li, Qi Ding, Yutuo Guo, Yu Wang, Kunqin He, Yaxin Liu, Lulu Peng:
An Ultra-Low Specific On-Resistance LDMOS With Segmented LOCOS In 0.18 μm BCD Process Platform. 1-3 - Xingchen Xin, Chunsheng Jiang, Hongying Chen:
A Continuous and Closed-Form Trans-Capacitance Model for Double-Gate Junctionless Transistors. 1-3 - Yue Shi, Jinyang He, Zhijian Zhang, Zekun Zhou, Bo Zhang:
A Cost-efficient Hybrid Gate Driver For SiC MOSFETs and IGBTs. 1-4 - Xunyu Li, Weiquan Hao, Zijin Pan, Runyu Miao, Albert Z. Wang:
Design for EMI Immunity and ESD Protection for Wearable and Flexible ICs (Invited). 1-2 - Yishan Zhang, Zhiyong Zhang, Chang Wu:
HierSyn: Fast Synthesis for Large Hierarchical Designs. 1-4 - Kunlong Li, Yunfei Dai, Zhen Li, Lingli Wang:
Permutation-Based Approximate Multiplier with High Accuracy. 1-4 - Giovanni De Micheli:
Logic Synthesis for Emerging Technologies. 1-4 - Xiaoyan Li, Zizheng Dong, Shuaipeng Li, Sai Gao, Jianfei Jiang, Guanghui He, Zhigang Mao:
MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5. 1-4 - Peerapat Phetpadriew, Bharatha Kumar Thangarasu, Nagarajan Mahalingam, Zhenghao Lu, Cher Ming Tan, Kiat Seng Yeo:
Concurrent Multiband CMOS Low Noise Amplifier Design for Internet of Things Applications. 1-4 - Ziyuan Chu, Zehua Chen, Taijia Zhang, Xinyi Li, Yuyin Sun, Yimeng Zhang, Yuming Zhang:
A Pseudo Short-circuit Adaptive Zero Current Detection Method for SIBTO in AMOLED Driver. 1-4 - Yufeng Guo, Kemeng Yang, Jing Chen, Man Li, Zhengfei Jiang, Jiafei Yao, Jun Zhang, Maolin Zhang:
Tradeoff Between the Breakdown Voltage and Specific On-Resistance of SOI RESURF LDMOS. 1-4 - Xiaohan Zhang, Tao Wang, Lingyun Shi, Di Hua, Zhiliang Hong:
A 7W, 2.5-5GHz Wideband GaN PA with Transformer-Based Matching Network. 1-4 - Yiwei Zhou, Weibo Li, Yongzhen Chen:
Nonlinear modeling of MIMO antenna array power amplifiers based on time-delay neural network. 1-4 - Xuanqi Li, Takashi Imagawa, Hiroyuki Ochi:
Finding All Solutions of Multi-terminal Numberlink Problem Utilizing Top-down ZDD Construction. 1-4 - Rui Jin, Niannian Ge, Ruifen Nie, Baohua Tian, Feng He, Xiamin Hao:
Optimal design of short circuit robustness for high voltage and high power IGBTs. 1-5 - Hanqi Gao, Jing Jin, Zhaolin Yang, Jianjun Zhou, Xiaoming Liu:
A 30GHz Bidirectional PA/LNA with Transformer-Based Switchable RC Matching Network. 1-4 - Jiarui Chen, Menglei Zhu, Shunyang Chen, Jiahui Zhu, Xiaoguo Huang, Guangqi Zhen:
A Low-Delay Self-Interference Cancellation Chip with Embeded Channel Sounding Ability. 1-3 - Jiahao Li, Wanlan Yang, Xing Zhou:
Numerical Characterization of a 5-Layer (Pt/Ta/TaO/AlO/W) RRAM Device. 1-4 - Mingyang Chen, Yunhui Qiu, Kaixiang Zhu, Lingli Wang:
An Automatic Optimization Method of Combinational Logic Loops in CGRA. 1-4 - Elaine Tang, Brian Lee, Chris Eom, Jake Jung:
A low power consumption and higher performance DDR5 receiver based on a direct feedback DFE and dedicated reference voltage for 1st TAP DFE. 1-3 - Hongchao Zhang, Yunfan Zuo:
A 2D Clock Interconnect Electromigration-Thermal Coupling Simulation Method Based on COMSOL. 1-4 - Tao Lu, Huan-Ming Wu, Tao Yin, Li-Yuan Liu, Wei Wang:
Loop Oscillation Analysis of MEMS Resonant Pressure Sensor Readout Circuit. 1-4 - Bo Yi, Haimeng Huang, Haoran Hu, MouFu Kong, Yilin Guo, Wenkun Shi, Junji Cheng, Hongqiang Yang:
Comprehensive Comparison of Temperature Performances for SiC Trench MOSFET with Integrated Side-wall Schottky Diode and Heterojunction. 1-4 - Feng-Wei Wang, Yunhao Fu, Yu-Chun Chang, Fei Wang, Dongxu Zhao:
Dual code channel hybrid readout circuit based on high precision Photoelectric encoders. 1-4 - Yuanxin Tian, Yuejun Zhang, Huihong Zhang, Liang Wen, Pengjun Wang, Zhiyi Li:
An Architecture of a Single-Event Tolerant D Flip-flop Using Full-Custom Design in 28nm Process. 1-4 - Hsientsai Wu:
Frontier Applications Research for Next-Generation Cardiovascular Health Monitoring Chip Design. 1-4 - Ran Bi, Baotong Zhang, Jianhuan Wang, Jianjun Zhang, Haixia Li, Ming Li:
TCAD Study on Strain Engineering in Vertical Channel Gate-all-around Transistor. 1-4 - Mengfan Xu, Yuejun Zhang, Huihong Zhang, Liang Wen, Tengfei Yuan, Pengjun Wang, Zhiyi Li:
Full-custom Design of Improved Carry Adder Circuit for CLBs. 1-4 - Aoxuan Wang, Jiale Sun, Hongliang Lu, Yi Zhu, Yuming Zhang:
Design and Optimization of Ternary Inverter using Face Tunnel Field-Effect Transistor. 1-4 - Yixuan Tong, Gengsheng Chen, Wei Xu:
DSSMNeRF: Depth Self-supervised MVS NeRF. 1-4 - Boming Su, Sikai Chen, Peiyin Cai, Tao Peng, Xiang Shuxia, Yi Wu, Guochi Huang:
A Broadband Voltage Controlled Oscillator with Multi-Band Output. 1-4 - Meng Li, Yixuan Hu, Tengyu Zhang, Renjie Wei, Yawen Zhang, Ru Huang, Runsheng Wang:
Not your father's stochastic computing (SC)! Efficient yet Accurate End-to-End SC Accelerator Design. 1-4 - Xueyan Zhang, Brian Lee, Chris Eom, Gaoyuan Pang, Jake Jung:
Pseudo differential DQS receiver for eliminating channel Hi-z noise. 1-3 - Yuan Wen, Zhijie Cai, Xingyu Tong, Min Wei, Jianli Chen:
Effective Analytical Placement for Advanced Face-to-Face-Bonded Circuit Designs. 1-4 - Xuewei Quan, Houren Ji, Xiaohu You, Chuan Zhang:
Efficient Search Path Reduction for NB-LDPC Codes with T-EMS Algorithm. 1-4 - Yue Lin, Hongtao Xu:
A Pattern Cancel DAC system design methodology for FMCW radar. 1-3 - Hanyang Wang, Zhonghan Shen, Hao Min:
An Ultra-Low-Power Temperature Sensor with an Accuracy of +0.6/-1 °C from-30 °C to 90 °C. 1-4 - Yi Chen, Tao Chen, Mengni Bie, Longmei Nan, Wei Li, Yiran Du:
A Domain-Specific DMA Structure for Per-channel Processing-based CNN Accelerator. 1-4 - Wenqiang Gong, Fang Zhou, Fen Ge:
A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture. 1-5 - Jiaxiang Li, Masao Yanagisawa, Youhua Shi:
An Area-Power-Efficient Multiplier-less Processing Element Design for CNN Accelerators. 1-4 - Jing-Yuan Wu, Mu-Yu Chen, Edward. Yi Chang:
Inversion-Mode InGaAs FinFETs for Logic and RF Applications. 1-3 - Honghong Long, Yu Bai, Yanze Li, Jian Wang, Jinmei Lai:
Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm. 1-4 - Ye Lin, Yang Xiao, Jingjing Lv, Li Du, Yuan Du:
A Dual-Mode Broadband Image Sensor Based on Graphene-CMOS Integration. 1-4 - Shenhao Jiang, Hao Chen, Shaowei Zhen, Keyu Li, Xin Chen, Liang Huang, Yongsheng Du, Bo Zhang:
Design of Smooth Mode Transition Buck-Boost Converter Based on Adaptive Offset Cancellation. 1-4 - Siqing Wu, Xinwei Yu, Xingtao Zhu, Fan Ye, Junyan Ren:
A Three-stage Analog Low-Frequency Drift Calibration and DC Offset Correction Circuit for Ultrasonic AFE. 1-4 - Hanyu Shi, Yuejun Zhang, Huihong Zhang, Qikang Li, Pengjun Wang:
Ternary Multiply-Accumulate Circuit Based on Domino Structure. 1-4 - Yande Jiang, Na Chen, Huiquan Wang, Guangda Zhang, Jun Xia, Xiaobo Yan:
A Speed Up Method towards DDR Subsystem Functional Verification in SoC. 1-4 - Zhenbo Rao, Yan Wang:
A Highly Automated and Rapid Datasheet Driven Empirical Modeling Process of SiC MOSFETs with High Accuracy and Robust Convergence. 1-4 - Zhaoyu Ai, Haiyun Liu, Xinyang Chen, Jing Feng, Yuxi Zhou, Moufu Kong:
A Novel Semi-superjunction SiC Trench MOSFET with Ultra-low Specific On-resistance. 1-4 - Xiaojun Zhang, Chenshi Zhu, Qin Han, Zhengrong Wang, Dexue Zhang:
A Low-complexity Max Unpooling Achitecture for CNNs. 1-4 - Mansun Chan:
Complementary Field-Effect Transistors: From Silicon to 2D Materials. 1-4 - Ho-Hin Tse, Zheng-Hong Zhong, Jyi-Tsong Lin:
An iTFET with Control Gate for Low Power Applications in RF and Digital Circuits. 1-4 - Chi-Tse Huang, An-Yeu Andy Wu:
Mitigating Non-ideality Issues of Analog Computing-In-Memory in DNN-based designs. 1-4 - Gaoyuan Pang, Brian Lee, Jake Jung, Chris Eom:
A Fast-Lock DLL with Prediction-Based Fast-Track FDL Structure for DDR5 SDRAMs. 1-4 - Cai Tian, Tianxiang Wu, Shunli Ma, Wenzhong Bao:
An Improved Delay Cell with Low Power Consumption and Strong Driving Capability. 1-4 - Xuran Ding, Guowang Su, Jun Zhang:
An Optimized Dataflow Based Accelerator for Sparse Convolutional Neural Networks. 1-4 - Guolong Fu, Shubin Liu, Li Tian, Zhangming Zhu, Yanbo Zhang:
A 77.8dB-SNDR 25MHz-BW 2nd-order NS Pipelined SAR ADC with 4th-order Gain-Error-Shaping. 1-4 - Maolin Pan, Luyu Wang, Qiang Wang, Penghao Zhang, Yuhang Wang, Min Xu:
Monolithic Logic Units based on DCFL Structure on p-GaN platform for GaN ICs. 1-4 - Haoyu Wu, Liyu Lin, Haodong Sun, Xiaoyang Zeng, Yun Chen:
A Decision-Based CORDIC Hardware for Arc Tangent Calculation. 1-4 - Changgu Yan, Yun Yin, Hongtao Xu:
Design of Multi-Mode Digital Signal Processing Circuit for Digital Transmitters. 1-4 - Hong-Chen Li, He Liu, Jie Li:
Cost-Efficient Soft Error Detection and Correction Flip-Flop Design for Nanoscale Technology. 1-4 - Jin Sun, Jiahao Hu, Ziqi Song, Qing Li, Dian He, Hujun Jia:
A Low Jitter Current-Mode Multiplying Delay-Locked Loop Applied to High-Precision TDC. 1-4 - Bingrong Lyu, Fan Ye, Junyan Ren:
A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology. 1-4 - Honglin Kuang, Yifan Zhao, Yi Sun, Jun Han:
General Vector Instruction Extension for GF(2m) Polynomial Operation in Post-quantum Cryptography. 1-4 - Lei Wu, Junyan Ren, Tianxiang Wu, Shunli Ma:
A 15GHz Class-C VCO with Two-stage Buffer in 0.15-μm GaAs. 1-4 - Rui Shi, Yunfan Zuo, Kelong Zhang, Hao Yan:
Hardware Acceleration Linear Matrix Solvor Based on FPGA. 1-4 - Shaoqi Yang, Xiaohuan Zhao, Kenie Xie, Xuepeng Zhan, Jixuan Wu, Jiezhi Chen:
One-shot Read Processing to Enhance Cold Data Retention in Charge-trap TLC 3D NAND Flash. 1-4 - Biwei Liu, Zhenyu Zhao, Jiageng Shi, Jie Zhou, Wencheng Jiang:
HDDB: a High Density Digital Waveform Storage Method. 1-7 - Peifang Wu, Yan Liu, Xi Feng, Hao Xu, Na Yan:
A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS. 1-4 - Yinyu Wang, Shuo Zhang, Chang Liu, Wenjun Tang, Wenxuan Tan, Qiaoling Tong, Desheng Zhang, Wanyang Wang, Run Min, Liying Zhu:
Current Balancing Strategy based on Threshold Midpoint Adjustment for Interleaved Constant Frequency Hysteresis Control Buck Converter. 1-4 - Zhuo Chen, Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Naifeng Jing:
ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator. 1-4 - Zhuangzhuang You, Xu Pang, Wenyue Zhou, Chao Ji, Xiaohu You, Chuan Zhang:
Low-Complexity Belief-selective Message Passing (BsMP) Detector for SCMA Systems. 1-4 - Yang Wang, Huihong Zhang, Yuejun Zhang, Hongshuai Wei, Pengjun Wang, Tengfei Yuan, Chengjie Wang:
High-Performance Rejection Sampling Hardware Circuit Design for Kyber. 1-4 - Wentao Zheng, Xiaohang Wang, Libo Qian:
A PSR Enhancement Scheme: An Overview of Feed-Forward Ripple Cancellation Technique. 1-4 - Jian Cui, Jian Zhang, Xuexiang Wang:
Lithographic Hotspot Detection Using Adaptive Squish Pattern Sampling Combined with Faster R-CNN. 1-4 - Xu Wang, Ke Chen, Chenghua Wang, Weiqiang Liu:
An Energy-efficient Approximate DCT Design for Image Processing (Invited). 1-4 - Feng Zou, Hai Huang, Ye Yuan, Yuhua Cheng:
An Integrated System of Blood Pressure and Electrocardiograph Recordings for Smart Home Healthcare Network. 1-4 - Yanze Li, Zeyu Sun, Jianfan Zhang, Zhichao Wei, Jian Wang, Jinmei Lai:
An Accurate Area Model for FPGA Circuits at Advanced Technologies. 1-4 - Shuoxiong Yang, Qingyang Dong, Wei Huang, Xin Jiang, Yang Wang, Weijun Luo:
A Compact 7-10 GHz GaN Low Noise Amplifier MMIC with Sub 0.3 dB Gain flatness. 1-4 - Kean Hong Tok, Jian Fu Zhang, James Brown, Zhigang Ji, Weidong Zhang:
Extracting statistical distributions of RTN originating from both acceptor-like and donor-like traps. 1-4 - Xinrui Guo, Lei Xu, Qifeng Cai, Shuo Liu, Junling Liu, Ming He:
Intelligent Multimodal Sensors Based on Novel Electronic-Ionic Bi2O2Se Semiconductors. 1-3 - Viktor Sverdlov, Siegfried Selberherr:
Charge and Spin Transport in Semiconductor Devices. 1-4 - Yigang Wei, Tianxiang Wu, Shunli Ma, Junyan Ren:
A Multi-channel 12-bits 100MS/s SAR ADC in 65nm CMOS. 1-4 - Wang Shi, Jian Cao, Guang Chen, Xuan Wang, Shengrong Liu, Yawei Ding:
Peripheral Hardware System Design for a Neuromorphic Chip. 1-4 - Jiangshan Zhao, Jiankun Huang, Yongzhen Chen, Jiangfeng Wu:
A Low-power Digital Automatic Gain Control Design in Wireless Communication Receivers. 1-4 - Yuanqi Wang, Kaichuang Shi, Lingli Wang:
An Enhanced Packing Algorithm for FPGA Architectures without Local Crossbar. 1-4 - Zengshi Wang, Chao Fu, Jun Han:
Coupled Data Prefetch and Cache Partitioning Scheme for CPU-Accelerator System. 1-4
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