Ming Chan

Electromigration and IR drop are challenging issues to understand and resolve in IC circuit verification. In our recent blog, Karen Chow and Joel Mercier explain how the conditions develop, and provides design teams with methods for eliminating or reducing their impact on circuit performance and reliability. https://lnkd.in/g2CdqyYW

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Mach42's AI-driven platform shortens the semiconductor design cycle. Supported by a high-caliber advisory board, their solutions revolutionize analog verification workflows. Read the Latest full News - https://lnkd.in/g6E-zCDb #Techedge #TechedgeAI #Mach42 #AI #Semiconductor #AnalogDesign #DeepLearning #CloudComputing #DesignVerification #ProductDevelopment #TechInnovation #SemiconductorDesign #MachineLearning #AIinSemiconductors #TechDisruption #ChipDesign #AnalogVerification #Engineering

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Happy Morning Today Post is STA: => Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface. => STA also considers the following types of paths for timing analysis: 📍 Clock path. A path from a clock input port or cell pin, through one or more buffers or inverters, to the clock pin of a sequential element; for data setup and hold checks. 📍 Clock-gating path. A path from an input port to a clock-gating element; for clock-gating setup and hold checks. 📍 Asynchronous path. A path from an input port to an asynchronous set or clear pin of a sequential element; for recovery and removal checks. #vlsi #semiconductor #hardware #sta #physicaldesign Intel Corporation, Qualcomm, AMD, Synopsys Inc, NVIDIA, NXP Semiconductors, Cadence Design Systems, Samsung Semiconductor, Micron Technology, Microchip Technology Inc., STMicroelectronics, Insemi Technology Services Pvt. Ltd., Arm, Marvell India

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📌Understanding FPGA and Its Design Flow💻 Watch : https://lnkd.in/gzcNkQFJ Field Programmable Gate Arrays (FPGAs) are versatile, reconfigurable hardware devices used in a wide range of applications, from data centers to automotive and industrial systems. Unlike ASICs, FPGAs allow designers to modify functionality even after deployment, offering flexibility and scalability. 🔍FPGA Design Flow: 1. Design Entry: Using HDL (Verilog/VHDL) to define logic. 2. Synthesis: Converting HDL code into a gate-level netlist. 3. Place and Route: Mapping logic to FPGA resources and routing signals. 4. Timing Analysis: Ensuring the design meets timing requirements. 5. Bitstream Generation: Creating the final configuration file to program the FPGA. 6. Programming: Uploading the bitstream to the FPGA for real-world operation. FPGAs provide rapid prototyping, lower upfront costs, and high performance for custom designs. Mastering the FPGA design flow is essential for hardware engineers aiming to innovate in today's tech-driven world. Check our Premium VLSI Courses : https://lnkd.in/gr8Ruqva Join VLSI Jobs : Whatsapp Channel : https://lnkd.in/dHsz2TZh Download VLSI FOR ALL Community App : https://lnkd.in/dB_QDcHT FREE Mentorship : https://wa.me/918218599381 Call us on (+91)-9643070368 Apple Users App Link : https://lnkd.in/dA_7YmYJ Write us on [email protected] #vlsiforall #vlsijobs #freshers #internship #vlsitraining #Semiconductor #Innovation #Technology #Beginners #Electronics #Engineering #VLSI #EmbeddedSystems #HardwareDesign #VLSI #APRFlow #PhysicalDesign #ChipDesign #Semiconductors #TechInnovation #FPGA #VLSI #HardwareDesign #Semiconductor #FPGADesignFlow #VLSIForAll #InnovationInTech

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Intel Arrow Lake loses DLVR bypass "Power Gate" profile in latest 0x112 microcode — chipmaker says the change will prevent "accidental misuse" https://lnkd.in/gAtijjsn #DLVR is basically a digital LDO design. It replaced inductive DC DC converter (#FIVR which many overclockers would be familiar with) that Intel Corporation used in previous chips and still uses in it's server platform. As per grapevine the design was opposed by some engineers who knew their power electronics but because it had VP level support it got pushed to the front - a true mark of Intel's decadent culture which has been around for decades, even though the results are only visible now. As per this article "DLVR is not technically an Arrow Lake-first technology. It was also featured on Raptor Lake but fused off for technical reasons." The technical reason was thay it didn't work as intended. And it is unlikely that it does now. Now Intel Corporation is probably desperately trying to put bandaid on the problem they have with 13th and 14th generation processors dying early as reported for months. The processors get a major performance hit at peak workload without pushing the voltage up. An integrated power regulator, like FIVR, works by providing high voltage only when it is needed. DLVR was supposed to do the same, but it probably doesn't work fast enough and burns too much power itself, so Intel's partner tried to fuse it off to keep performance (and ironically power also) good, but that probably kills the chips over time by voltage overstess.Keeping the voltage low kills performance. This is a desperate move, if DLVR actually worked, why was it fused off in the first place?

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A free-to-use (not open-source), Industrial grade, complete SystemVerilog IEEE-1800-2017 simulator. Also supports VHDL.

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What are the 6 key difference between OSAT and Chip fab ? 🚀 Core Function Chip Fab: The primary focus is on the front-end processes, which include creating the actual silicon wafer and fabricating the circuitry on it using photolithography, etching, doping, and deposition. OSAT: OSAT providers handle the back-end processes, such as assembly, packaging, and testing of the semiconductor chips. They take the manufactured silicon wafers from chip fabs, cut them into individual chips, package them, and conduct final testing. 🚀 Type of Work Chip Fab: Involves highly sophisticated front-end fabrication work, including creating the intricate patterns on silicon wafers that form the circuits inside a chip. This requires expensive equipment like lithography machines and cleanroom facilities. OSAT: In contrast, OSAT focuses on assembly and testing, where the wafers are cut into individual dies, connected to external leads, and encapsulated to form a durable and functional package. They also perform extensive reliability and stress testing. 🚀 Facilities and Equipment Chip Fab: Requires extremely high-tech, capital-intensive facilities, including specialized cleanrooms and complex equipment such as extreme ultraviolet (EUV) lithography systems, deposition tools, and ion implanters. OSAT: OSAT facilities are typically less capital-intensive than fabs but still require advanced machinery for dicing, wire bonding, flip-chip bonding, and automated testing. They also need some degree of cleanroom environment for the packaging process. 🚀 Technology Focus Chip Fab: Focuses on semiconductor fabrication technologies like photolithography, CVD and atomic layer etching (ALE). The goal is to make smaller, more powerful, and efficient chips. OSAT: Focuses on assembly and packaging technologies, such as wire bonding, die bonding, flip-chip, and wafer-level packaging, along with electrical and environmental testing. The goal is to create durable, reliable, and compact chip packages that can be integrated into end devices. 🚀 Business Model Chip Fab: The business is focused on producing wafers and making advancements in chip performance and efficiency. OSAT: OSAT providers work in a service-oriented model, primarily supporting fabless companies and IDMs. They focus on packaging and testing, often working on a contractual basis for multiple clients. 🚀 Final Product Chip Fab: Delivers a wafer with chips etched on it, which still needs to be separated, packaged, and tested. OSAT: Provides final, tested, and packaged semiconductor devices ready to be integrated into electronics such as smartphones, computers, or cars. -------------------- P.S: If you like writings like these, we have compiled 100s of such questions in our book- The semiconductor Saga- a book that teaches you everything about semiconductors in simple words. Link in comments.

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What are the 6 key difference between OSAT and Chip fab ? 🚀 Core Function Chip Fab: The primary focus is on the front-end processes, which include creating the actual silicon wafer and fabricating the circuitry on it using photolithography, etching, doping, and deposition. OSAT: OSAT providers handle the back-end processes, such as assembly, packaging, and testing of the semiconductor chips. They take the manufactured silicon wafers from chip fabs, cut them into individual chips, package them, and conduct final testing. 🚀 Type of Work Chip Fab: Involves highly sophisticated front-end fabrication work, including creating the intricate patterns on silicon wafers that form the circuits inside a chip. This requires expensive equipment like lithography machines and cleanroom facilities. OSAT: In contrast, OSAT focuses on assembly and testing, where the wafers are cut into individual dies, connected to external leads, and encapsulated to form a durable and functional package. They also perform extensive reliability and stress testing. 🚀 Facilities and Equipment Chip Fab: Requires extremely high-tech, capital-intensive facilities, including specialized cleanrooms and complex equipment such as extreme ultraviolet (EUV) lithography systems, deposition tools, and ion implanters. OSAT: OSAT facilities are typically less capital-intensive than fabs but still require advanced machinery for dicing, wire bonding, flip-chip bonding, and automated testing. They also need some degree of cleanroom environment for the packaging process. 🚀 Technology Focus Chip Fab: Focuses on semiconductor fabrication technologies like photolithography, CVD and atomic layer etching (ALE). The goal is to make smaller, more powerful, and efficient chips. OSAT: Focuses on assembly and packaging technologies, such as wire bonding, die bonding, flip-chip, and wafer-level packaging, along with electrical and environmental testing. The goal is to create durable, reliable, and compact chip packages that can be integrated into end devices. 🚀 Business Model Chip Fab: The business is focused on producing wafers and making advancements in chip performance and efficiency. OSAT: OSAT providers work in a service-oriented model, primarily supporting fabless companies and IDMs. They focus on packaging and testing, often working on a contractual basis for multiple clients. 🚀 Final Product Chip Fab: Delivers a wafer with chips etched on it, which still needs to be separated, packaged, and tested. OSAT: Provides final, tested, and packaged semiconductor devices ready to be integrated into electronics such as smartphones, computers, or cars. -------------------- P.S: If you like writings like these, we have compiled 100s of such questions in our book- The semiconductor Saga- a book that teaches you everything about semiconductors in simple words. Link in comments.

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This month's safety matters #EZBlog series is about the requirement for on chip separation to allow a claim of HFT=1. So, if you are looking for a blog on IEC 61508-2:2010 Annex E, this is for you!

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To ensure smooth communication across various UVC's in a UVM testbench, classes are required. To seamlessly communicate between those UVM class, several methods and approach needs to be adopted. This not only increases the efficiency of the testbench but also makes sure the process flow of UVM is followed. [1] Transaction Level Modelling (TLM): TLM provides a bidirectional means of communication between sequencer class and driver class. It also enable code reuse without any further modification of testbench code. The similar approach is adopted in SystemVerilog testbench using mailbox where the communication is established between a generator and driver class through put/get function calls. [2] Methodical Function / Task Calls: In SystemVerilog/UVM, all the functions and tasks defined are by default automatic and that's why it's quite easy and portable to call them from separate places from the interacting classes. [3] Domain Synchronisation and Phase Jumping: This technique needs to be used cautiously otherwise there are chances of race condition. Basically if we want to synchronize between a reset phase and configure phase, we can use phase jumping. [4] Virtual Interface: Virtual interfaces acts as references to physical interfaces and play a crucial role in facilitating communication between dynamic driver and monitor classes and the static DUT. [5] Callback Mechanism: UVM provides callback mechanism that enables one class to register a callback function with another class. This allows for event driven communication where specific action like error injection trigger callbacks leading to dynamic responses. [6] Scoreboard and Analysis Port: An analysis port of an monitor connected to an agent which in turn connected to Scoreboard. Scoreboard also consist of two components mainly Predictor and Evaluator. Predictor can consist of golden reference data similar to that of DUT and send it to evaluator for comparison. [7] Configuration Mechanism: To parameterize a particular UVM environment, uvm_config_db has been used for flow of the entries via configuration table through its set/get, exist and wait_modified methods. Similarly usage of uvm_resource_db needs to be used as it support extra methods like get_by_type, get_by_name, read_by_name, set_anonymous, etc. [8] Built in phases: UVM has in built phases which is a structure of Directed Acyclic Graph (DAC) and the flow of phases takes care of the structure and the interconnecting components in the TB across various classes. [9] User defined phases: UVM also supports the use of phase jumping and creation of domains with the help of custom phases to establish communication among several classes. [10] Arbitration Mechanism: UVM has several inbuilt arbitration scheme to take care of sequence item flow into driver through sequencer. [11] Interrupt Handling: grab() and lock() methods can be used #vlsi #asic #electronics #semiconductorindustry

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Building tiny tech titans? Boundary optimization is your secret weapon! This VLSI trick trims the fat from your chip design, making it smaller, faster, and more power-efficient. #VLSI #engineering #electronics #chipdesign #hardware #embeddedsystems Read more : https://lnkd.in/e2BUw_gf  #IoT #efficiency #performance #innovation #technology #future #engineeringlife #learnengineering #makerspace #techcareers #stem #futureoftech #electronicsdesign #embeddeddev #engineeringstudent #electronicsengineer #electricalengineering

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The soon-to-come Ottawa Semiconductor Fab in Canada, a vast III-V semiconductor tech campus, is set to be a hub for semiconductor manufacturing, research, academia, and related amenities. SILICAN's report stresses the need to enhance domestic chip capacity to safeguard Canada's security and economy amidst geopolitical shifts, urging investments to connect chip producers and end-users, while calling for a robust talent pool in the industry. CMC Microsystems emphasizes securing advanced device supply, protecting IP, and boosting onshore manufacturing through initiatives like FABriC, aiming to create intelligent sensor technology and enhance Canada's competitive advantage and supply chain security, particularly in Ottawa's Compound Semiconductor sandbox. Various partnership opportunities are envisioned to propel compound semiconductor innovation, support academia, develop technology like GaN power systems, foster EV battery advancements, and bolster autonomous vehicle technologies within Ottawa's flourishing semiconductor ecosystem. #Canada #semiconductor #chip #GaN #EV #AI #power #research #innovation #manufacturing #technology #sensor #compoundsemiconductor https://lnkd.in/evsN-6HN

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What are considered parasitic junctions in core analog layout, can be silicon saving junctions when it comes to ESD robustness. It’s often these hidden junctions that we don’t usually consider in day to day layout, that become the backbones of our ESD strategies. This is the sort of detail that we discuss during our ESD layout course; the next one of which, runs from Tuesday 21st May, through Friday 24th, delivered remotely. If you’re interested in participating or hearing more, please have your manager or HR department reach out to James Telfer for information on pricing and availability.

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What is analog IP? Analog IP is a crucial part of every IC (Integrated Circuit) or SoC (System on Chip), but can be overlooked until late in the development schedule as it provides system control and management functions. Typical analog IP includes: Analog-to-Digital Converters (ADCs), Digital-to-Analog Converters (DACs), Power-On-Reset (POR), Low Drop-Out (LDO) regulators, Glitch detectors and Oscillators. The main challenge with traditional analog IP is that it needs to be redesigned for every process, and often the correct configuration is not available off-the-shelf, and so manual work is required to fit the design to the application. How does Agile Analog help? Agile Analog has developed a unique technology which transforms the way analog designs are created and delivered. Using our technology, designs are created specifically for your application, based on your requirements using our latest rules-based AI design recipes. The design is optimized for your process, and our repeatable, systematic methodology enables us to recreate and modify your design with complete reassurance. For each of the key issues above, the Composa technology helps address these concerns: * Performance - optimized specifically for your application needs, giving you optimal PPA * Feature set - add or remove features easily to save area * Area and aspect ratio - adjust the aspect ratio and performance/area trade-offs at IDP delivery time * Process - select any process or process variant, be confident the performance is optimal for the transistor types available * Configuration and changes - select your own metal stack, process configuration and design parameters to meet your needs * Licensing model - simple licensing model works with your needs to balance up-front fee vs royalty * Changes required to the IP - changes can be added easily up to IDP sign-off  * Cost basis - drastically reduce the cost of your product by integrating more analog IP on-chip * External components - make trade-offs to optimize the balance of internal and external components * Quality - our unique delivery checker, auto-generation and validation approach assure the highest quality deliverables * Test silicon - Composa has been proven on test silicon, and we continue to run example blocks on multiple shuttles * Support model - our comprehensive application support team taps into our architects to answer your questions * Design knowledge - all our designs are codified in Composa to ensure that the IP simple to support and modify * Delivery time - we deliver initial views early in the process and ensure changes are well understood prior to final delivery Agile Analog is dedicated to delivering premium IP solutions through our innovative Composa technology. https://lnkd.in/gN8_fpn5

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Guarantee signal integrity with a thorough time-domain reflectometry PCB analysis that guides board prototyping and ensures performance for each manufactured board.

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Watch : https://lnkd.in/gGqGrtcp The full form of FPGA is “Field Programmable Gate Array”. It contains ten thousand to more than a million logic gates with programmable interconnection. Programmable interconnections are available for users or designers to perform given functions easily. A typical model FPGA chip is shown in the given figure. There are I/O blocks, which are designed and numbered according to function. For each module of logic level composition, there are CLB’s (Configurable Logic Blocks). CLB performs the logic operation given to the module. The inter connection between CLB and I/O blocks are made with the help of horizontal routing channels, vertical routing channels and PSM (Programmable Multiplexers). The number of CLB it contains only decides the complexity of FPGA. The functionality of CLB’s and PSM are designed by VHDL or any other hardware descriptive language. After programming, CLB and PSM are placed on chip and connected with each other with routing channels. Advantages It requires very small time; starting from design process to functional chip. No physical manufacturing steps are involved in it. The only disadvantage is, it is costly than other styles. Join VLSI Jobs : Whatsapp Channel : https://lnkd.in/dHsz2TZh Download VLSI FOR ALL Community App : https://lnkd.in/dB_QDcHT FREE Mentorship : https://wa.me/918218599381 Call us on (+91)-9643070368 Apple Users App Link : https://lnkd.in/dA_7YmYJ Write us on [email protected] #vlsiforall #vlsijobs #freshers #internship #vlsitraining #Semiconductor #Innovation #Technology #Beginners #Electronics #Engineering #VLSI #EmbeddedSystems #HardwareDesign

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Canada's semiconductor industry is gaining momentum, but challenges remain. In a recent EE Times | Electronic Engineering Times article by Gary Hilson, our CEO Chris Walker shares his insights on the country's efforts to bolster its chip sector: "What is needed is a virtuous cycle that will both propel and perpetuate leadership in the sector," says Walker. Consistent funding and fostering a vibrant ecosystem where "people move around and ideas flow" should be the emphasis. At Untether AI, we're committed to driving innovation and contributing to a thriving tech ecosystem, right here in Canada. Learn more about the industry's response to recent funding announcements at https://lnkd.in/gWqSgKAP. Marie-Josée Turgeon, C2MI Gordon Harling, CMC Microsystems Stephane Tremblay, IBM Bromont . . . #cdntech #ai #inference #acceleration #semiconductor #investment #funding

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What is a System on Chip (SoC) in the world of Semiconductor Chips? 🚀 Imagine a bustling city with various buildings serving different purposes: a central processing unit (CPU) like a city hall, memory units like libraries, a graphics processing unit (GPU) like a theater, and communication modules like post offices. These components, though essential, would require intricate wiring and infrastructure to function together. Now, picture all these components being integrated into a single, tiny chip. This is the essence of a System on a Chip (SoC). It's like condensing an entire city into a single, powerful microchip. 🚀 What is an SoC? An SoC is an integrated circuit that integrates most or all components of a computer or other electronic system onto a single chip. This includes: 1) Central Processing Unit (CPU): The brain of the operation, responsible for executing instructions.  2) Memory: Stores data and instructions.  3) Graphics Processing Unit (GPU): Handles visual tasks, like displaying images and videos.  4) Input/Output (I/O) Interfaces: Connects the SoC to external devices, like keyboards, mice, and displays.  5) Communication Modules: Enables wireless connectivity (Wi-Fi, Bluetooth, cellular) and wired connections (Ethernet).  6) Other specialized components: Depending on the device, an SoC may include additional components like digital signal processors (DSPs) for audio and video processing, or neural network accelerators for artificial intelligence. 🚀 Why SoCs? 1) Miniaturization: Smaller devices with more capabilities.  2) Lower Power Consumption: Less energy is required to power a single chip.  3) Increased Performance: Faster processing speeds and better efficiency.  4) Reduced Cost: Manufacturing a single chip is generally more cost-effective.  5) Improved Reliability: Fewer connections and components mean fewer potential points of failure. 🚀 Real-world Examples 1) Smartphones: The heart of every smartphone is an SoC that integrates a CPU, GPU, memory, communication modules, and other components.  2) Gaming Consoles: High-performance SoCs power modern gaming consoles, enabling stunning graphics and immersive gameplay. 3) Internet of Things (IoT) Devices: SoCs enable IoT devices like smart speakers, thermostats, and security cameras to connect to the internet and perform various tasks.  4) Autonomous Vehicles: Self-driving cars rely on powerful SoCs to process sensor data and make real-time decisions.   🚀 In conclusion, SoCs have revolutionized the electronics industry by enabling the creation of smaller, more powerful, and energy-efficient devices. As technology continues to advance, SoCs will play an increasingly important role in shaping the future of electronics. For all semiconductor and AI related content, follow TechoVedas ------ Read our book The semiconductor Saga: A book that teaches you about semiconductors in simple words. Link in comments.

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